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data sheet october 2003 orca ? or3tp12 field-programmable system chip (fpsc) embedded master/target pci interface introduction lattice has developed a solution for designers who need the many advantages of an fpga-based design implementation coupled with the high band- width of the industry-standard pci interface. the orca or3tp12 fpsc provides a full-featured 33/50/66 mhz, 32-/64-bit pci interface, fully designed and tested, in hardware, plus fpga logic f or user-programmable functions. pci local bus pci local bus, or simply, pci bus, has become an industry-standard interface protocol for use in appli- cations ranging from desktop pc busing to high- bandwidth backplanes in networking and communi- cations equipment. the pci bus speci cation* pro- vides for both 5 v and 3.3 v signaling environments. the pci interface clock speed is speci ed in the r ange from dc to 66 mhz with detailed speci cations at 33 mhz and 66 mhz as well as recommendations f or 50 mhz operation. data paths are de ned as either 32-bit or 64-bit. these data path and frequency combinations allow for the peak data transfer rates described in table 1. ta b le 1. pci local bus data rates the pci bus is electrically speci ed so that no glue logic is required to interface to the bus?pci devices interface directly to the pci bus. other features include registers for device and subsystem identi ca- tion and autocon guration, support for 64-bit addressing, and multimaster capability that allows any pci bus master access to any pci bus target. pci bus core highlights implemented in an orca series 3 base array, dis- placing the bottom four rows of 18 columns. core is a well-tested asic model. fully compliant to revision 2.1 of pci local bus speci cation (and designed for revision 2.2). * pci local bus speci cation rev. 2.1, pci sig, june 1, 1995. clock frequency (mhz) data path width (bits) p eak data rate (mbytes) 33 32 132 33 64 264 66 32 264 66 64 528 tab le 2. orca pci fpsc solutions?available fpga resources * the embedded core and interface comprise approximately 85k standard-cell asic gates in addition to these usable gates. the usa b le gate counts range from a logic-only gate count to a gate count assuming 30% of the pfus/slics being used as rams. the logic-onl y gate count includes each pfu/slic (counted as 108 gates per pfu/slic), including 12 gates per lut/ff pair (eight per pfu), and 12 gates per slic/ff pair (one per pfu). each of the four pios per pic is counted as 16 gates (two ffs, fast-capture latch, output logic, c lk drivers, and i/o buffers). pfus used as ram are counted at four gates per bit, with each pfu capable of implementing a 32 4 ram (or 512 gates) per pfu. device usable gates * number of luts number of registers max user ram max user i/os array size number of pfus or3tp12 30k?60k 2016 2636 32k 187 14 18 252
ta b le of contents contents page contents page orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 2 lattice semiconductor i ntroduction ...............................................................1 pci local bus .....................................................1 pci bus core highlights ............................................1 fpsc highlights ........................................................4 software support .......................................................4 description .................................................................5 what is an fpsc? ...............................................5 fpsc overview ...................................................5 tfpsc gate counting .........................................5 fpga/embedded core interface ........................5 fpsc design kit .................................................6 isplever development system ........................6 fpga logic overview .........................................6 plc logic ...........................................................7 pic logic ............................................................7 system features .................................................7 routing ................................................................8 configuration ......................................................8 more series 3 information ...................................8 or3tp12 overview ...................................................8 device layout .....................................................8 or3tp12 pci bus core overview ......................8 pci bus interface ................................................8 embedded core options/fpga configuration ..................................................10 pci bus core detailed description .........................11 pci bus commands .........................................11 pci protocol fundamentals ..............................14 pci bus pin information ....................................16 embedded core/fpga interface signal descriptions ...................................................19 embedded core/fpga interface signal locations ........................................................27 embedded core configuration options ...........29 embedded core/fpga fifo interface operation summary .......................................31 pci bus core master controller detailed description ...........................................................32 fifo interface overview ...................................32 master write operation .....................................33 master read operation ....................................41 pci bus core target controller detailed description ...........................................................51 target fifo interface ........................................51 target write operation .....................................51 target read operation .....................................63 clocking options at fpga/embedded core boundary ........................................................78 configuration space of the pci bus core ........80 fpsc configuration ...........................................84 fpga configuration target controller data format ..................................................................86 using isplever to generate configuration ram data .................................86 fpga configuration data frame ......................86 bit stream error checking .......................................88 fpga configuration modes .....................................88 absolute maximum ratings .....................................89 recommended operating conditions .....................89 electrical characteristics .........................................90 timing characteristics .............................................91 description ........................................................91 pfu timing ........................................................92 plc timing ........................................................92 slic timing .......................................................92 pio timing ........................................................92 special function timing ....................................92 clock timing .....................................................92 configuration timing .........................................92 readback timing ..............................................92 input/output buffer measurement conditions ........97 output buffer characteristics ..................................98 estimating power dissipation ..................................99 pin information ......................................................100 package thermal characteristics summary .........113 ja .................................................................113 jc .................................................................113 jc .................................................................113 jb .................................................................113 fpga maximum junction temperature ..........113 package thermal characteristics ..........................114 package coplanarity .............................................114 package parasitics ................................................114 package outline diagrams ....................................116 terms and definitions .....................................116 256-pin pbga .................................................117 352-pin pbga .................................................118 ordering information ..............................................119
lucent technologies inc. 3 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core highlights (continued) operates at pci bus speeds up to 66 mhz. comprises two independent controllers for master and target. meets/exceeds all requirements for picmg * hot swap friendly silicon, full hot swap model, per the compactpci * hot swap speci cation, picmg 2.1 r1.0. pci sig hot-plug (r1.0) compliant. f our internal fifos individually buffer both directions of both the master and target interfaces: ? both master fifos are 64 bits wide by 32 bits deep. ? both target fifos are 64 bits wide by 16 bits deep. capable of no-wait-state, full-burst pci transfers in either direction, on either the master or target inter- f ace. dual 32-bit data paths extend into the fpga logic, permitting full-bandwidth, simultaneous bidi- rectional data transfers of up to 264 mbytes/s to be sustained inde nitely. can be con gured to provide either two 32-bit buses (one in each direction) to be multiplexed between master and target, or four independent 16-bit buses. provides many hardware options in the pci bus core that are set during fpga logic con guration. operates within the requirements of the pci 5 v and 3.3 v signaling environments, allowing the same device to be used in 5 v or 3.3 v pci systems. fpga is recon gurable via the pci interface con gu- r ation space (as well as conventionally), allowing the fpga to be eld-updated to meet late-breaking requirements of emerging protocols. master: ? generates all de ned command codes except interrupt acknowledge and special cycle. ? capable of acting as the system's con guration agent by booting up with the master logic enabled. ? provides multiple options to increase pci bus bandwidth. t arget: ? responds legally to most command codes: inter- r upt acknowledge, special cycle, and reserved commands ignored; memory read multiple and line handled as memory read; memory write and invalidate handled as memory write. ? implements target abort, disconnect, retry, and w ait cycles. ? handles delayed transactions. ? handles fast back-to-back transactions. ? supports programmable latency timer control. ? method of handling wait-states is programmable to allow tailoring to different target data access latencies. ? decodes at medium speed. supports dual-address cycles (both as master and t arget). supports all six base address registers (bars), as either memory (32-bit or 64-bit) or i/o. any legal page size can be independently speci ed for each bar during fpga con guration. provides versatile clocking capabilities with fpga clocks sourced from pci bus clock or elsewhere. fifo interface buffers asynchronous clock domains between the pci interface and fpga-based logic. pci interface timing: meets or exceeds 33 mhz, 50 mhz, and 66 mhz pci requirements. standard 256-byte pci con guration space: ? class code, revision id. ? latency timer. ? cache line size. ? subsystem id. ? subsystem vendor id. ? maximum latency, minimum grant. ? interrupt line. ? hot plug/hot swap capability. * compactpci and picmg are registered trademarks of the pci industrial computer manufacturers group. p arameter 33 mhz 50 mhz 66 mhz device clock = > out 11.0 ns 7.5 ns 6.0 ns device setup time 7.0 ns 4.5 ns 3.0 ns board prop. delay 10.0 ns 6.5 ns 5.0 ns board clock skew 2.0 ns 1.5 ns 1.0 ns t otal budget 30.0 ns 20.0 ns 15.0 ns
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 4 lucent technologies inc. lattice semiconductor pci bus core highlights (continued) generates interrupts on intan as directed by the fpga. provisions for 64-bit pci bus capability in 352-pin pbga package. a utomatically detects 5 v or 3.3 v pci bus signaling environment and provides appropriate i/o signal clamping. pinout compatible with the orca pci master/target customer solution core v2.0 for or2c/txxa or orca series 3 fpgas. ideally suited for such applications as: ? pci-based graphics/video/multimedia. ? bridges to isa/eisa/mca, lan, scsi, ethernet, a tm, or other bus architectures. ? high-bandwidth data transfer in proprietary sys- tems. fpsc highlights implemented as an embedded core into the advanced series 3+ orca fpsc architecture. allows the user to integrate the core with up to 60k gates of programmable logic, all in one device, and provides up to 187 user i/o pins in addition to the pci interface pins. fpga portion retains all of the features of the orca series 3 fpga architecture: ? high-performance, cost-effective, 0.3 m 4-level metal technology, with a migration plan to 0.25 m technology. ? twin-quad programmable function unit (pfu) architecture with eight 16-bit look-up tables (luts) per pfu, organized in two nibbles for use in nibble- or byte-wide functions. allows for mixed arithmetic and logic functions in a single pfu. ? softwired luts (swl) allow fast cascading of up to three levels of lut logic in a single pfu for up to 40% speed improvement (-5 speed grade). ? supplemental logic and interconnect cell (slic) provides 3-statable buffers, up to 10-bit decoder, and pa l *-like and-or-invert (aoi) in each programmable logic cell (plc). ? up to three expressclk inputs allow extremely f ast clocking of signals on- and off-chip plus access to internal general clock routing. ? dual-use microprocessor interface (mpi) can be used for con guration, readback, device control, and device status, as well as for a general-pur- pose interface to the fpga. glueless interface to i960 ? and po w erpc ? processors with user-con g- urable address space provided. ? programmable clock manager (pcm) adjusts clock phase and duty cycle for input clock rates from 5 mhz to 120 mhz. the pcm may be com- bined with fpga logic to create complex func- tions, such as digital phase-locked loops (dpll), frequency counters, and frequency synthesizers or clock doublers. two pcms are provided per- device. ? true internal 3-state, bidirectional buses with sim- ple control provided by the slic. ? 32 4 ram per pfu, con gurable as single or dual-port at >170 mhz (-5 speed). create large, f ast ram/rom blocks (128 8 in only eight pfus) using the slic decoders as bank drivers. ? built-in boundary scan ( ieee 1149.1 jtag) and ts_all testability function to 3-state all i/o pins. high-speed on-chip interface provided between fpga logic and embedded core to reduce bottle- necks typically found when interfacing off-chip. supported in two packages: 256-pin pbga, and 352-pin pbga (64-bit pci in 352-pin pbga only). software support supported by isplever software and third-party cae tools for implementing orca series 3+ devices and simulation/timing analysis with embedded pci b us core. pci bus core con guration options and simulation models generated by fpsc con guration manager utility in orca fpsc design kit software. timing constraints provided for interface between pci bus core and fpga logic. * pa l is a trademark of advanced micro devices, inc. ? i960 is a registered trademark of intel corporation. ? po w erpc is a registered trademark of international business machines corporation. ieee is a registered trademark of the institute of electrical and electronics engineers, inc.
lucent technologies inc. 5 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor description what is an fpsc? fpscs, or eld-programmable system chips, are devices that combine eld-programmable logic with asic or mask-programmed logic on a single device. fpscs provide the time to market and e xibility of fpgas, the design effort savings of using soft intellec- tual property (ip) cores, and the speed, design density, and economy of asics. fpsc overview lattice?s series 3+ fpscs are created from series 3 orca fpgas. to create a series 3+ fpsc, several rows of programmable logic cells (see fpga logic overview section for fpga logic details) are removed from a series 3 orca fpga, and the area is replaced with an embedded logic core. other than replacing some fpga gates with asic gates, at greater than 10:1 ef ciency, none of the fpga functionality is changed?all of the series 3 fpga capability is retained: mpi, pcms, boundary scan, etc. the rows of programmable logic are replaced at the bottom of the device, allowing pins on the bottom and sides of the replaced rows to be used as i/o pins for the embedded core. the remainder of the device pins retain their fpga functionality as do special function fpga pins within the embedded core area. tfpsc gate counting the total gate count for an fpsc is the sum of its embedded core (standard-cell/asic gates) and its fpga gates. because fpga gates are generally e xpressed as a usable range with a nominal value, the total fpsc gate count is sometimes expressed in the same manner. standard cell/asic gates are, however, 10 to 25 times more silicon area ef cient than fpga gates. therefore, an fpsc with an embedded function is gate equivalent to an fpga with a much larger gate count. fpga/embedded core interface the interface between the fpga logic and the embed- ded core is designed to look like fpga i/os from the fpga side, simplifying interface signal routing and pro- viding a uni ed approach with general fpga design. effectively, the fpga is designed as if signals were going off of the device to the embedded core, but the on-chip interface is much faster than going off-chip and requires less power. all of the delays for the interface are precharacterized and accounted for in the isplever software. clock spines also can pass across the fpga/embed- ded core boundary. this allows for fast, low-skew clock- ing between the fpga and the embedded core. many of the special signals from the fpga, such as done and global set/reset, are also available to the embed- ded core, making it possible to fully integrate the embedded core with the fpga as a system. f or even greater system e xibility, fpga con guration rams are available for use by the embedded core. this allows for user-programmable options in the embedded core, in turn allowing for greater e xibility. multiple embedded core con gurations may be designed into a single device with user-programmable control over which con gurations are implemented, as well as the capability to change core functionality simply by recon- guring the device.
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 6 lucent technologies inc. lattice semiconductor description (continued) fpsc design kit development is facilitated by an fpsc design kit which, together with isplever and third-party synthe- sis and simulation engines, provides all software and documentation required to design and verify an fpsc implementation. included in the kit are the fpsc con- guration manager, ve r ilog * and vhdl * simulation models, all necessary synthesis libraries, and complete online documentation. the kit's software couples with isplever software under the control of the isplever control center (ofcc), providing a seamless fpsc design environment. more information can be obtained by visiting the orca website or contacting a local sales of ce, both listed on the last page of this docu- ment. isplever development system the isplever development system is used to pro- cess a design from a netlist to a con gured fpsc. this system is used to map a design onto the orca archi- tecture and then place and route it using isplever software?s timing-driven tools. the development system also includes interfaces to, and libraries for, other popu- lar cae tools for design entry, synthesis, simulation, and timing analysis. the isplever development system interfaces to front-end design entry tools and provides the tools to produce a con gured fpsc. in the design ow , the user de nes the functionality of the fpga portion of the fpsc and embedded core settings at design entry stage. the embedded core options determine the fpsc functionality. f ollowing design entry, the development system?s map, place, and route tools translate the netlist into a routed fpsc. a static timing analysis tool is provided to deter- mine design speed, and a back-annotated netlist can be created to allow simulation. simulation output les from isplever are also compatible with many third- party analysis tools. its bit stream generator is then used to generate the con guration data which is loaded into the fpsc?s internal con guration ram. when using the fpsc con guration manager, the user selects options that affect the functionality of the fpsc. combined with the front-end tools, isplever pro- duces con guration data that implements the various logic and routing options discussed in this data sheet. fpga logic overview orca series 3 fpga logic is a new generation of sram-based fpga logic built on the successful series 2 fpga line, with enhancements and innova- tions geared toward today?s high-speed designs and tomorrow?s systems on a single chip. designed from the start to be synthesis friendly and to reduce place and route times while maintaining the complete routability of the orca series 2 devices, the series 3 more than doubles the logic available in each logic b lock and incorporates system-level features that can further reduce logic requirements and increase system speed. orca series 3 devices contain many new pat- ented enhancements and are offered in a variety of packages, speed grades, and temperature ranges. orca series 3 fpga logic consists of three basic ele- ments: plcs, programmable input/output cells (pics), and system-level features. an array of plcs is sur- rounded by pics. each plc contains a pfu, a slic, local routing resources, and con guration ram. most of the fpga logic is performed in the pfu, but decod- ers, pa l -like functions, and 3-state buffering can be performed in the slic. the pics provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, and other functions on two output signals. some of the sys- tem-level functions include the new microprocessor interface ( mpi ) and the pcm . * ve r ilog and vhdl are registered trademarks of cadance design systems, inc.
lucent technologies inc. 7 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor description (continued) plc logic each pfu within a plc contains eight 4-input (16-bit) luts, eight latches/ ip- ops (ffs), and one additional ip- op that may be used independently or with arith- metic functions. the pfu is organized in a twin-quad fashion: two sets of four luts and ffs that can be controlled indepen- dently. luts may also be combined for use in arith- metic functions using fast-carry chain logic in either 4-bit or 8-bit modes. the carry-out of either mode may be registered in the ninth ff for pipelining. each pfu may also be con gured as a synchronous 32 4 single- or dual-port ram or rom. the ffs (or latches) may obtain input from lut outputs or directly from invertible pfu inputs, or they can be tied high or tied low. the ffs also have programmable clock polarity, clock enables, and local set/reset. the slic is connected to plc routing resources and to the outputs of the pfu. it contains 3-state, bidirec- tional buffers and logic to perform up to a 10-bit and function for decoding, or an and-or with optional invert aoi to perform pa l -like functions. the 3-state drivers in the slic and their direct connections to the pfu outputs make fast, true 3-state buses possible within the fpga logic, reducing required routing and allowing for real-world system performance. pic logic the series 3t pic addresses the demand for ever- increasing system clock speeds. each pic contains f our programmable inputs/outputs (pios) and routing resources. on the input side, each pio contains a fast- capture latch that is clocked by an expressclk . this latch is followed by a latch/ff that is clocked by a sys- tem clock from the internal general clock routing. the combination provides for very low setup requirements and zero-hold times for signals coming on-chip. it may also be used to demultiplex an input signal, such as a m ultiplexed address/data signal, and register the sig- nals without explicitly building a demultiplexer. two input signals are available to the plc array from each pio, and the orca series 2 capability to use any input pin as a clock or other global input is maintained. on the output side of each pio, two outputs from the plc array can be routed to each output ip- op, and logic can be associated with each i/o pad. the output logic associated with each pad allows for multiplexing of output signals and other functions of two output sig- nals. the output ff, in combination with output signal multi- plexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. the i/o b uffer associated with each pad is the same as the orca series 3t buffer. system features the series 3 also provides system-level functionality by means of its dual-use microprocessor interface (mpi) and its innovative pcm. these functional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in today?s high-speed systems. since these and all other series 3t features are available in every series 3+ fpsc, they can also interface to the embedded core providing f or easier system integration.
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 8 lucent technologies inc. lattice semiconductor description (continued) routing the abundant routing resources of orca series 3 fpga logic are organized to route signals individually or as buses with related control signals. clocks are routed on a low-skew, high-speed distribution network and may be sourced from plc logic, externally from any i/o pad, or from the very fast expressclk pins. expressclks may be glitchlessly and independently enabled and disabled with a programmable control sig- nal using the new stopclk feature. the improved pic routing resources are now similar to the patented intra- plc routing resources and provide great e xibility in moving signals to and from the pios. this e xibility translates into an improved capability to route designs at the required speeds when the i/o signals have been locked to speci c pins. con guration the fpga logic?s functionality is determined by internal con guration ram. the fpga logic?s internal initializa- tion/con guration circuitry loads the con guration data at powerup or under system control. the ram is loaded by using one of several con guration sources, including serial eeprom, the microprocessor inter- f ace, or the embedded function core. more series 3 information f or more information on series 3 fpgas, please refer to the series 3 fpga data sheet, available on the lat- tice website. or3tp12 overview device layout the or3tp12 fpsc provides a pci local bus core (with fifos) combined with fpga logic. the device is based on a 3.3 v or3t55 fpga. the or3t55 has an 18 18 array of plcs. for the or3tp12, the bottom f our rows of plcs in the array were replaced with the embedded pci bus core. figure 1 shows a schematic view of the or3tp12. the upper portion of the device is a 14 18 array of plcs surrounded on the left, top, and right by programmable input/output cells (pics). at the bottom of the plc array are interface cells connect- ing to the embedded core region. the embedded core region contains the pci bus functionality of the device. it is surrounded on the left, bottom, and right by pci b us dedicated i/os as well as power and special func- tion fpga pins. also shown are the interquad routing b locks (hiq, viq) present in the series 3t fpga devices. system-level functions (located in the corners of the plc array), routing resources, and con guration ram are not shown in figure 1. or3tp12 pci bus core overview the or3tp12 embedded core comprises a pci bus interface with independent master and target control- lers, fifo memories, control logic for data buffering, a dual-/quad-port interface to the fpga logic which per- fo r ms data packing and multiplexing, and logic to sup- port the embedded core and fpga con guration. a detailed description of all of the features and functional- ity of the or3tp12 embedded core is provided in the f ollowing sections. pci bus interface the or3tp12 pci bus core is compliant to revision 2.1 of the pci local bus speci cation. it is capable of no-wait-state, full-burst operation at all of the rate/data width combinations described in table 1 as well as at a 50 mhz speci cation that provides a speed increase ov er the 33 mhz speci cation and a larger bus loading capability than the 66 mhz speci cation. the or3tp12 operates in either the 3.3 v or 5 v pci sig- naling environment and is automatically con gured for the appropriate environment by a pci bus vio pin. independent master and target controllers are pro- vided for use in systems requiring master/target or tar- get only operation. six 32-bit base address registers (bars) are provided for decoding the address space of the pci device, and these six 32-bit registers can be combined in pairs to produce 64-bit bars. dual- address cycles are supported when the pci bus is either 32 or 64 bits wide. the bars work in either the i/o or the memory space of the device and can be con- gured as prefetchable or nonprefetchable.
lucent technologies inc. 9 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor or3tp12 overview (continued) 5-4489(f).b figure 1. or3tp12 array pl9 pl8 pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl13 pl12 pl11 pr12 pr11 pr9 pr8 pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr13 pr14 pr10 rmid pt1 pt2 pt3 pt4 pt5 pt6 pt7 pt8 pt9 pt11 pt12 r1c1 r1c2 r1c3 r1c4 r1c5 r1c6 r1c7 r1c8 r1c9 r1c10 r1c18 r1c17 r1c16 r1c15 r1c14 r1c13 r1c12 r1c11 pt13 pt14 pt15 pt16 pt17 pt18 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pb9 pb11 pb12 pl14 pb13 pb14 pb15 pb16 pb17 pb18 pl10 pb10 pt10 r2c1 r2c2 r2c3 r2c4 r2c5 r2c6 r2c7 r2c8 r2c9 r2c10 r3c1 r3c2 r3c3 r3c4 r3c5 r3c6 r3c7 r3c8 r3c9 r3c10 r4c1 r4c2 r4c3 r4c4 r4c5 r4c6 r4c7 r4c8 r4c9 r4c10 r5c1 r5c2 r5c3 r5c4 r5c5 r5c6 r5c7 r5c8 r5c9 r5c10 r6c1 r6c2 r6c3 r6c4 r6c5 r6c6 r6c7 r6c8 r6c9 r6c10 r7c1 r7c2 r7c3 r7c4 r7c5 r7c6 r7c7 r7c8 r7c9 r7c10 r8c1 r8c2 r8c3 r8c4 r8c5 r8c6 r8c7 r8c8 r8c9 r8c10 r9c1 r9c2 r9c3 r9c4 r9c5 r9c6 r9c7 r9c8 r9c9 r9c10 r10c1 r10c2 r10c3 r10c4 r10c5 r10c6 r10c7 r10c8 r10c9 r10c10 r2c18 r2c17 r2c16 r2c15 r2c14 r2c13 r2c12 r2c11 r3c18 r3c17 r13c16 r3c15 r3c14 r3c13 r3c12 r3c11 r4c18 r4c17 r4c16 r4c15 r4c14 r4c13 r4c12 r4c11 r5c18 r5c17 r5c16 r5c15 r5c14 r5c13 r5c12 r5c11 r6c18 r6c17 r6c16 r6c15 r6c14 r6c13 r6c12 r6c11 r7c18 r7c17 r7c16 r7c15 r7c14 r7c13 r7c12 r7c11 r8c18 r8c17 r8c16 r8c15 r8c14 r8c13 r8c12 r8c11 r9c18 r9c17 r9c16 r9c15 r9c14 r9c13 r9c12 r9c11 r10c18 r10c17 r10c16 r10c15 r10c14 r10c13 r10c12 r10c11 r14c18 r14c17 r14c16 r14c15 r14c14 r14c13 r14c12 r14c11 r13c18 r13c17 r13c16 r13c15 r13c14 r13c13 r13c12 r13c11 r12c18 r12c17 r12c16 r12c15 r12c14 r12c13 r12c12 r12c11 r11c18 r11c17 r11c16 r11c15 r11c14 r11c13 r11c12 r11c11 r14c10 r14c9 r14c8 r14c7 r14c6 r14c5 r14c4 r14c3 r14c2 r14c1 r13c10 r13c9 r13c8 r13c7 r13c6 r13c5 r13c4 r13c3 r13c2 r13c1 r12c10 r12c9 r12c8 r12c7 r12c6 r12c5 r12c4 r12c3 r12c2 r12c1 r11c10 r11c9 r11c8 r11c7 r11c6 r11c5 r11c4 r11c3 r11c2 r11c1 hiq lmid embedded core area bmidt tmid viq
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 10 lucent technologies inc. lattice semiconductor or3tp12 overview (continued) independent data paths exist for the master and target fifo interface. this allows for separate operation of master and target functions, and the capability for a master to transfer data to a target on the same device. in dual-port mode, the master and target fifo interfaces share two unidirectional 32-bit data paths between the fifos and the fpga logic. this provides for full-rate transfers in 32-bit pci bus operation, when operating the fpga application and pci bus at the same frequency. quad-port mode provides two independent 16-bit data paths for each fifo interface: one for read data and the other for write data. this mode allows for simultaneous operations on either the master or target controller. diagrams for dual-port and quad-port operation are shown in figure 2. embedded core options/fpga con guration in addition to the series 3 fpga con guration modes, the or3tp12 can also be con gured via the pci bus. con- guration as discussed here covers two operations. there is con guration of the fpga logic, and there is con gu- r ation of the options available in the embedded core. both are accomplished through the fpga con guration process. readback of fpga and pci bus core options is also possible using the pci bus or series 3t fpga read- back modes. at powerup, the pci bus core will be functional with a default pci bus con guration space, as de ned in the pci bus 2.1 speci cation, even prior to an initial con guration of the fpga logic. figure 2. orca or3tp12 pci fpsc block diagram 5-6368.b 5-6368.a quad-port mode dual-port mode 73 user i/o pads or3t series fpga 14 rows x 18 columns 57 user i/o pads 57 user i/o pads pci master/target interface pci bus data control and multiplexing 32 32 64-bit x 16 deep fifo target 64-bit x 16 deep fifo target 64-bit x 32 deep fifo master 64-bit x 32 deep fifo master 73 user i/o pads or3t series fpga 14 rows x 18 columns 57 user i/o pads 57 user i/o pads pci master/target interface pci bus data control and multiplexing 16 16 16 16 64-bit x 16 deep fifo target 64-bit x 16 deep fifo target 64-bit x 32 deep fifo master 64-bit x 32 deep fifo master
lucent technologies inc. 11 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core detailed description the following sections describe the operation of the embedded pci bus core interface. pci bus commands the pci bus core supports all commands required by the pci speci cation. the following table describes each command. subsequent sections will describe the protocols in which the commands are used. ta b le 3. pci bus command descriptions command code (binary) command or3tp12 master generates or3tp12 targ et accepts description 0000 interrupt acknowledge ?? only implemented by master agents that interface to the system cpu and as target by agents that incorporate the system interrupt controller. 0001 special cycle ? ? target ignores, per pci speci cation section 3.7.2. 0010 i/o read ? target : single accesses only, with bursts disconnected after rst data phase. dela y ed mode ( deltrn = 0): te r minates the initial access with a retry, recording internally the pci address and byte enables for processing by the fpga application. subse- quent pci accesses occurring before the fpga application loads the target read fifo continues to result in retries. after the target read fifo is loaded by the fpga applica- tion, the next read access that matches the stored parame- ters disconnects with the fpga supplied data and the t arget read logic is cleared. nondela y ed mode ( deltrn = 1, trb ur stpendn = 0): accepted access inserts wait-states up to the initial latency count (16 or 32 clocks depending on the option selected in the fpsc con guration manager). during the wait-states, the fpga application processes the read request and transfers data into the target read fifos. if read data is transferred into the target read fifos before the latency count expires, this read data is transferred to the pci bus during initial request. if not, the pci address, byte enables, and target read data remain stored in the target controller. the next access that matches the stored address and byte enables disconnects with the fpga supplied data, and the t arget read logic is cleared. master: single and burst operations are allowed.
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 12 lucent technologies inc. lattice semiconductor 0011 i/o write ? targ et: single accesses only, with bursts disconnected after rst data phase. dela y ed_mode ( deltrn = 0): te r minates the initial access with a retry, recording internally the pci address, byte enables, and write data for processing by the fpga appli- cation. subsequent pci accesses occurring before the fpga application accepts the target write data will result in retries. after the target write data is received by the fpga application, the next i/o write access that matches the stored parameters (pci address, byte enables, and write data) disconnects with data, and the target write logic is cleared. nondela y ed mode ( deltrn = 1, trb ur stpendn = 0): access posts write data into the target write fifos and discon- nects with data. the fpga application then processes the i/o write request and transfer data from target write fifos. master: single and burst operations are allowed. 0100 (reserved) ? ? target ignores, per pci speci cation section 3.1.1. 0101 (reserved) ? ? target ignores, per pci speci cation section 3.1.1. 0110 memory read ? target : single and burst accesses are allowed. the amount of data transferred will depend on either the external pci master terminating the read transaction, or the target read fifos becoming empty. dela y ed_mode ( deltrn = 0): te r minates the initial access with a retry, recording internally the pci address and byte enables for processing by the fpga application. subse- quent pci accesses occurring before the fpga application loads the target read fifo continues to result in retries. after the target read fifo is loaded by the fpga applica- tion, the next read access that matches the stored parame- ters begins transfer of the fpga supplied data. nondela y ed mode ( deltrn = 1, trb ur stpendn = 0): accepted access inserts wait-states up to the initial latency count (16 or 32 clocks depending on the option selected in the fpsc con guration manager). during the wait-states, the fpga application processes the read request and transfer data into the target read fifos. if read data is transferred into the target read fifos before the latency count expires, this read data is transferred to the pci bus during initial request. if not, the pci address, byte enables, and target read data are stored in the target controller. the next access that matches the stored address and byte enables begins transfer of the fpga supplied data. master : single and burst operations are allowed. command code (binary) command or3tp12 master generates or3tp12 targ et accepts description pci bus core detailed description (continued) ta b le 3. pci bus command descriptions (continued)
lucent technologies inc. 13 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor 0111 memory write ? fully implemented. targ et: writes are posted, bursting is allowed, and wait- states generation is controllable. when the target write fifo is full, the next data phase will be disconnected with- out data ( twburstpendn = 1), or up to eight wait-states can be inserted ( twburstpendn = 0). after the pci bus transac- tion completes and the fpga application empties the tar- get write fifo, the target write logic is cleared. master: single and burst operations are allowed. 1000 (reserved) ? ? target ignores, per pci speci cation section 3.1.1. 1001 (reserved) ? ? target ignores, per pci speci cation section 3.1.1. 1010 con guration read ? targ et: bursting is disallowed, and no wait-states are gen- erated. target disconnects with data on rst data word. the fpga portion of the device is not involved in con guration transactions. master: single and burst operations are allowed. 1011 con guration write ? fully implemented. targ et: bursting is disallowed, and no wait-states are gen- erated. target disconnects with data on rst data word. the fpga portion of the device is not involved in con guration transactions. master: single and burst operations are allowed. 1100 memory read multiple ? fully implemented. both the master and the target treat this instruction the same as a memory read (4?b0110); the user?s fpga logic is responsible for ensuring that the mas- ter operation meets the special requirement that the read request ends on a cacheline boundary. 1101 dual-access cycle ? fully implemented. per pci speci cation 2.1, section 3.10.1, the pci bus core (as a master) automatically con- ve r ts a 64-bit address to a 32-bit address if the upper 32 bits are all zeros. 1110 memory read line ? fully implemented. both the master and the target treat this instruction the same as a memory read (0110). the user?s fpga logic is responsible for ensuring that the master operation meets the special requirement that the read request continues to the next cacheline boundary. 1111 memory write and invalidate ? fully implemented. both the master and the target treat this instruction the same as a memory write (0111); the user?s fpga logic is responsible for ensuring that the master operation meets the special requirement that writes of com- plete cachelines, with all byte enables, are performed. command code (binary) command or3tp12 master generates or3tp12 targ et accepts description pci bus core detailed description (continued) ta b le 3. pci bus command descriptions (continued)
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 14 lucent technologies inc. lattice semiconductor pci bus core detailed description (continued) pci protocol fundamentals basic transfer control the following paragraphs describe various aspects of the pci protocol and the way they are handled by the pci bus core. addressing. the pci speci cation de nes three types of address spaces. the rst, con guration address space, is a physical address space that is intended as a means for powerup software to identify agents and allocate them address space. the second, i/o address space, is intended for mapping i/o control functions. the third, memory address spaces, is intended for bulk data transfer. it has features to facilitate this, such as special commands for cache implementation, large page sizes, and mechanisms for prefetching. the pci b us core handles all three address space types as both a master and a target. byte alignment. on all write operations (con guration, i/o, and memory) for both the pci bus core?s master and target functions, byte enables are fully imple- mented from/to the fpga interface. note, however, that even though the pci bus core implements the abil- ity to control byte enables for the memory write and invalidate instruction, the pci speci cation requires that this instruction assert all byte enables, and this is the fpga application?s responsibility. on read opera- tions, the utility of byte enables is more dubious since the data must be enroute from the pci bus target to master, at the time that the corresponding byte enables are enroute from the pci bus master to target (unless w ait-states are inserted). the pci bus core, therefore, does not implement full-byte enable control for target reads, and limited for master reads. f or the or3tp12, byte enables on master read burst operations must always be asserted; nonburst master reads may manipulate the byte enables. byte enables on target read operations are ignored, in accordance with pci speci cation 2.1, section 3.2.3. all master b urst read and write addresses must be aligned on 64-bit boundaries. single read and write addresses can be aligned on 32-bit boundaries. device selection (devseln) the target is responsible for decoding the address of a m aster?s request by asserting the pci bus signal devseln . devseln may be asserted one, two, or three clocks after the address phrase of a transaction, corre- sponding to fast, medium, or slow decode, respectively. the pci bus core?s target is capable of performing a medium-speed decode response. the decode response speed has a signi cant impact on the overall latency and bandwidth of nonburst pci transactions. its impact decreases greatly for burst transactions, partic- ularly for burst lengths of the size of the pci bus core?s fifos. address/data stepping stepping is an optional feature added to the pci speci- cation to accommodate agents whose bus drive capa- bility is insuf cient to handle large groups of signals changing state in one clock cycle. continuous stepping allows weak drivers multiple cycles for signal transition. discrete stepping partitions the bus into two or more g roups of bits that transition on successive clock cycles. however, stepping exacts a heavy toll on perfor- mance, cutting maximum bandwidth by at least 50% and increasing latency. the pci core is designed for maximum throughput with high-performance buffers, so stepping is unnecessary and not implemented. the w ait cycle control, bit seven of the command register, is therefore hardwired to a 0. interrupt acknowledge the interrupt acknowledge command is a read by the system cpu implicitly addressed to the system inter- r upt controller. other agents, including the pci bus core, are not required to implement this instruction; the pci bus core?s master does not generate it, and its tar- get ignores it. arbitration parking the pci speci cation requires that all master agents properly handle bus parking, which means that when that agent receives an asserted gntn without the agent having asserted its reqn , the agent still must drive sig- nal par and buses ad and c_ben to a stable value. the pci bus core meets this requirement.
lucent technologies inc. 15 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core detailed description (continued) p arity the pci bus core implements all required and optional f eatures, including the following: master generates parity on all addresses placed on the bus. sending agent generates parity on all data placed on the bus. t arget calculates parity on all addresses received from the bus. receiving agent calculates parity on all data received from the bus. the detected parity error bit in the status register is set whenever an agent calculates corrupted parity. the signal perrn is generated whenever an agent calculates corrupted data parity and the parity error response bit is set in the pci command register. the signal serrn is generated whenever an agent calculates a corrupt address parity. 66 mhz operation the pci bus core is fully compliant to pci speci cation requirements at all clock rates up to 66 mhz. all 33 mhz requirements are also met. timing budget the pci bus core?s timing budget is summarized in ta b le 4. note that the 66 mhz timing requirements only allow 5 ns for signal proagation (t prop ), as compared to 10 ns at 33 mhz. the effect of the reduction is to reduce also the number of agents that the bus can sup- port, although the actual number is not speci ed in the pci speci cation and is dependent on the design of the hardware components. the four components of the timing budget are t val (valid output delay), t prop (propagation time), t su (input setup time), and t skew (clock skew); of these, only t val and t su are controlled by the pci component, and t prop and t skew are sys- tem parameters. table 4 includes a third column (also shown in the pci speci cation); this column indicates the performance attainable if all 66 mhz requirements are met except t prop = 10 ns, which is the 33 mhz v alue. in this case, the total budget increases from 15 ns (66 mhz) to 20 ns (50 mhz). ta b le 4. timing budgets 64-bit addressing the pci bus core fully supports 64-bit addressing, whether or not the pci bus core is con gured to utilize the 64-bit data extension. when the pci bus core is a 64-bit target being addressed by 64-bit master, the pci b us core will decode the address one cycle faster so that dual-address operation will have no performance impact; see pci speci cation 2.1, section 3.10.1 for details. section 3.10.1 of the pci speci cation 2.1 also states that a master that supports 64-bit addressing must nevertheless generate requests utilizing a single address instead of a dual-address when the upper 32 bits are all zeros. this shortens the request time by one cycle when communicating with 32-bit targets. fifo memories and control the or3tp12 embedded core contains four fifo memories and supporting control logic. two fifos are f or the master fifo interface data and two for the tar- get fifo interface data. these fifos are con gured to operate in 64-bit mode and can also carry byte enable bits on a per-byte basis (e.g., a 64-bit fifo actually carries 64 bits of data and eight byte enable bits for a total of 72 bits). all fifos have two relevant ags which e xtend into the fpga logic for user application (e.g., a t arget read fifo on the fpga side has full and full-4 ags extending into the fpga logic). clocking for the fpga port of all fifos is e xible, with options for dif- f erent clocks for the master and target fifos, all sourced by the fpga logic. timing element 33 mhz 50 mhz 66 mhz unit cycle time 30.0 20.0 15.0 ns v alid output delay 11.0 7.5 6.0 ns propagation time 10.0 6.5 5.0 ns input setup time 7.0 4.5 3.0 ns clock skew 2.0 1.5 1.0 ns
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 16 lucent technologies inc. lattice semiconductor pci bus core detailed description (continued) pci bus pin information this section describes signals on the pci bus interface and at the embedded core/fpga interface. some signal de nitions change name and location based on the mode of operation. modes of operation are described following the signal descriptions. pci bus signal package pin locations can be found in table 42 through . ta b le 5. pci bus pin descriptions symbol i/o description system pins clk i clock. provides timing for all transactions on the pci bus and is an input to the or3tp12 device. all pci signals, except r stn and intan , are sampled on the rising edge of clk , and all other pci bus timing parameters are de ned with respect to this edge. clk operates up to 66 mhz, and the minimum frequency is dc. r stn i reset. an active-low signal used to reset the entire pci bus. r stn is asynchronous to clk . when asserted, all pci output signals are 3-stated. address and data pins ad[31:0] i/o address and data. multiplexed on the same pci pins. a pci bus transaction con- sists of an address phase followed by one or more data phases. during data phases, ad[7:0] contain the least signi cant byte and ad[31:24] con- tain the most signi cant byte. during memory commands, the ad[31:2] lines spec- ify the address and ad[1:0] specify the type of bursting sequence to use. the table below outlines the bursting sequence based on the values of ad[1:0] for the target. ad[1:0] bursting sequence . 00 linear incrementing accepted by the target. 01 target disconnect after rst transfer. 10 target disconnect after rst transfer. 11 target disconnect after rst transfer. c_ben[3:0] i/o bus command and byte enables. active-low signals multiplexed on the same pci pins. during the address phase of a transaction, c_ben[3:0] de ne the bus command. during the data phase, c_ben[3:0] are used as byte enables. the byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data. par i/o p arity. speci es even parity across ad[31:0] and c_ben[3:0] . par is stable and v alid one clock after the address phase. for data phases, par is stable and valid one clock after irdyn is asserted on a write transaction or trdyn is asserted on a read transaction. once par is valid, it remains valid until one clock after the comple- tion of the current data phase. the master drives par for address and write data phases; the target drives par for read data phases. interface control pins framen i/o cycle frame. an active-low signal driven by the current master to indicate the beginning and duration of an access. framen is asserted to indicate a bus transac- tion is beginning. while framen is asserted, data transfers continue. when framen is deasserted, the transaction is in the nal phase or has completed.
lucent technologies inc. 17 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core detailed description (continued) ta b le 5. pci bus pin descriptions (continued) symbol i/o description interface control pins (continued) irdyn i/o initiator ready. an active-low signal indicating the bus master?s ability to complete the current data phase of the transaction. irdyn is used in conjunction with trdyn . a data phase is completed on any clock cycle during which both irdyn and trdyn are asserted. during a write, irdyn indicates that valid data from the master is present on the ad bu s. during a read, it indicates that the master is prepared to accept data. w ait cycles are inserted until both irdyn and trdyn are asserted together. trdyn i/o ta rg et ready. an active-low signal asserted to indicate the readiness of the tar- get?s agent to complete the current data phase of the transaction. trdyn is used in conjunction with irdyn . a data phase is completed on any clock where both trdyn and irdyn are sampled active. during reads, trdyn indicates that valid data from the t arget is present on the ad bu s. during write cycles, trdyn indicates that the target is prepared to accept data. stopn i/o stop. indicates that the current target is requesting the master to stop the current transaction. idsel i initialization device select. used as a chip select during pci con guration read and write transactions. generally, the user ties idsel to one of the upper 24 address lines, ad[31:8] . devseln i/o device select. an active-low signal indicating that a target device on the bus has been selected. as an output, it indicates that the driving device has decoded its address as the target of the current access. arbitration pins (for bus master only) reqn o request. an active-low signal that indicates to the arbiter that the asserting agent desires use of the bus. in the or3tp12, this signal is asserted when the or3tp12 master controller needs access to the pci bus. gntn i grant. an active-low signal that indicates to the or3tp12 master that access to the pci bus has been granted. error reporting pins perrn i/o p arity error. an active-low signal for the reporting of data parity errors during all pci transactions except a special cycle. the perrn pin is a sustained 3-state signal and must be driven active by the agent receiving data two clocks following the data when a data parity error is detected. the minimum duration of perrn is one clock for each data phase that a data parity error is detected. if sequential data phases each have a data parity error, the perrn signal will be asserted for more than a single clock. perrn is driven high for one clock before being 3-stated. perrn is not asserted until it has claimed the access by asserting devseln and completed a data phase. serrn o system error. an active-low signal pulsed by agents to report errors other than data parity. serrn is sampled every clk edge, so any agent asserting serrn m ust ensure it is valid for at least one clock period. for example, serrn can be asserted if an abort sequence is detected by the master, or an address parity error is detected by the target.
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 18 lucent technologies inc. lattice semiconductor pci bus core detailed description (continued) ta b le 5. pci bus pin descriptions (continued) symbol i/o description interrupt pins intan o pci interrupt. the or3tp12 asserts this active-low signal when it requests an interrupt from the pci compliant interrupt controller. 64-bit bus extension pins ad[63:32] i/o 64-bit address and data. these signals provide the upper 32 bits of address and data when in pci 64-bit operation. during a 64-bit address phase (when using the dual-address command (dac) and when req64n is asserted), the upper 32-bit address bits are transferred. during a data phase, the data is valid when req64n and ack64n are both asserted. otherwise, these bits are 3-stated. c_ben[7:4] i/o byte enables. these are the upper four, active-low, bus command and byte enables when in pci 64-bit operation. during a 64-bit address phase (when using the dual-address command (dac) and when req64n is asserted), the bus com- mand is transferred. during a data phase, these bits are the active-low byte enables f or data bits ad[63:32] . otherwise, these bits are 3-stated. req64n i/o request 64-bit transfer. this active-low signal is asserted by the current bus master to indicate that it desires to transfer data using 64 bits. ack64n i/o acknowledge 64-bit transfer. within its decoded address space (devseln asserted), the target drives this signal active-low indicating that it can perform 64-bit data transfers, in response to a received active-low req64n . ack64n has the same timing as devseln in 32-bit transfers. par64n i/o upper double-word parity . the even parity bit that covers ad[63:32] and c_ben[7:4] . par64n is valid one clock after the initial address phase when req64n is asserted and the dual-address command (dac) is indicated on c_ben[3:0] . it is also valid the clock cycle after the second address phase of a dac command when req64n is asserted. for data phases, par64n is stable and valid one clock after irdyn is asserted on a write transaction or trdyn is asserted on a read transaction. once par64n is valid, it remains valid until one clock after the completion of the cur- rent data phase. on 64-bit pci buses, the master drives par64n for address and write data phases; the target drives par64n for read data phases. hot swap function pins enumn o enumeration. active-low signal that noti es the system host that the card has been freshly inserted or is about to be extracted. the system host can then either install (for insertion) or deactivate (for extraction) the card?s software driver to adjust for the change in system con guration. ledn o led . active-low open-drain signal that drives a external blue led, indicating that removal of the card is permitted. this signal is asserted low whenever the led on/ off (loo) bit in the hot swap control and status register (hsscr) is asserted high. ejectsw i eject switch. active-high signal that indicates that the card?s ejector handle is unseated. this signals that the operator has freshly inserted the card, or will extract the card when the blue led illuminates. if not used, tie high or low. vio i pci bus signaling environment voltage. this input indicates to the pci bus core the signaling environment being employed on the pci bus. the input is tied to the appropriate voltage supply (either 5.0 v or 3.3 v).
lucent technologies inc. 19 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core detailed description (continued) embedded core/fpga interface signal descriptions in table 6, an input refers to a signal o wing into the fpga logic (out of the embedded core) and an output refers to a signal o wing out of the fpga logic (into the embedded core). ta b le 6. embedded core/fpga interface signals symbol i/o description clock domain master general signals fpga_mbusyn o fpga master is busy. the fpga application asserts this active-low signal to indicate to the master to assert the reqn signal until fpga_mbusyn becomes inactive or the target disconnects. this is helpful in pci applications in which master has multiple high-priority transactions to be performed. once asserted, this signal needs to remain asserted for a minimum of two pciclk cycles. pciclk fpga_msyserror i fpga master cycle aborted by pci target. the master controller asserts this active-high signal as an indication that the current cycle to the pci bus has been aborted. fclk * mstatecntr[3:0] i master state counter. indicates the current state of the master fifo inter- f ace. details of the master fifo interface can be found in the pci bus core master controller detailed description section of this data sheet. fclk * m foclrn o master fifo clear. this active-low signal is asynchronously asserted by the fpga application to clear the master address, read, and write fifos, along with mstatecntr . this signal does not reset the master controllers pci state machine within the embedded core, and therefore it is not recommended to be used to terminate the current pci transaction. ? m_ready i master logic ready. this active-high signal indicates that the master fifo interface to the fpga logic is ready. this signal will be inactive during pci bus resets and master fifo clears. fclk * master fifo address and command control signals maenn o master command/start address/read burst length enable. this is an ac- tive-low signal used to register the master command word, read burst length, and pci start address into the master controller registers. the type of data transferred from the fpga application will depend on the current state of mstatecntr and the interface mode (quad-port or dual-port). further description is provided in the command/address setup section (see page 33) of the pci bus core master controller detailed description section. fclk * ma_fulln i master address register full flag. this active-low signal indicates that the master address register is full and no new pci master transactions can be ac- cepted from the fpga application. this flag is cleared when the master trans- action is completed on the pci bus. for master writes, ma_fulln is cleared when all write data has been transferred to the external target. for master reads, ma_fulln is cleared when all read data has been received from the ex- ternal target, although all read data may not have been transferred to the fpga application. fclk * * the source of the clock ( fclk1 or fclk2 ) for the fifo interface (master or target) is selected in the fpsc con guration manager.
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 20 lucent technologies inc. lattice semiconductor symbol i/o description clock domain master write data fifo signals mwlastcycn o master write last data cycle. this active-low signal has two functions: a. it is asserted low to indicate that the current master start address word is the nal portion being sent. it can be asserted prior to any address portion being transferred, indicating to use the previous stored address in the selected master holding register. maenn must be asserted with mwlastcycn during the nal address word. b. it is asserted low to indicate that the accompanying master write data is the nal data for this operation. mwdataenn m ust be asserted with mwlastcycn during the nal data word. fclk * mwdataenn o master write fifo data enable. this active-low signal enables the registering of data bus mwdata (quad-port mode) or datafmfpga (dual-port mode) during master write operations into the master write data fifos. mwdataenn should not be asserted when the master write data fifos are full, or data may be lost. fclk * mwpcihold o master write pci bus hold. for master write transfers on the pci bus, this signal delays the start of the transfer (i.e., reqn asserted) on the pci bus, allowing the fpga application to ll the master write data fifo. the transac- tion will begin when mwpcihold is deasserted or the master write data fifo becomes full. mwpcihold should be deasserted before mwlastcycn is asserted, and needs to remain asserted for a minimum of two pciclk cycles. pciclk mw_afulln i master write data fifo almost full flag. this active-low signal indicates that only four more empty 64-bit locations remain in the master write data fifo. fclk * mw_fulln i master write data fifo full flag. this active-low signal indicates that the master write data fifo is full. mwdataenn should never be asserted when mw_fulln is active. fclk * * the source of the clock ( fclk1 or fclk2 ) for the fifo interface (master or target) is selected in the fpsc con guration manager. pci bus core detailed description (continued) ta b le 6. embedded core/fpga interface signals (continued)
lucent technologies inc. 21 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor symbol i/o description clock domain master write data fifo signals (continued) mwdata[17:0] (quad-port mode) or datafmfp- gax[3:0] , datafmfpga[31:0] (dual-port mode) o depending on the or3tp12 con guration, only one of these buses will be av ailable to the fpga application. for master operations, these buses will carry the same information, but in different sizes and different bit lanes as sum- marized below: quad-p or t mode dual-p or t mode a. master command. control data decoded by the master controller and fifo interface repeat burst length: mwdata[17] datafmfpgax[3] dual-address indication: mwdata[16] datafmfpgax[2] unused: mwdata[15:13] datafmfpga[31:29] holding reg. selector: mwdata[12] datafmfpga[28] master rd. byte enables: mwdata[11:4] datafmfpga[27:20] master command code: mwdata[3:0] datafmfpga[19:16] b. master start address: 32- or 64-bit pci start address. unused: mwdata[17:16] datafmfpgax[3:0] address: mwdata[15:0] datafmfpga[31:0] c. master read burst count (18 bits): number of 64-bit words. burst length[17:16]: mwdata[17:16] datafmfpgax[1:0] burst length[15:0]: mwdata[15:0] datafmfpga[15:0] d. master write data: write data to pci bus. write enables: mwdata[17:16] datafmfpgax[3:0] data: mwdata[15:0] datafmfpga[31:0] fclk * master read data fifo signals mrdataenn o master read fifo data output enable. this active-low signal enables data from the master read data fifos onto bus mrdata (quad-port mode) or datatofpga (dual-port mode, fifo_sel = 0). mrdataenn must never be asserted if the master read fifo is empty ( mr_emptyn = 0) fclk * mrdata[17:0] (quad-port mode) or datatofpgax[3:0 ], datatofpga[31:0] (dual-port mode) i depending on the or3tp12 con guration, only one of these buses will be av ailable to the fpga application. for master operations, these buses will carry the same information, but in different sizes as summarized below: quad-p or t mode dual-p or t mode ( f o_sel = 0) master read data (16/32 bits) unused: mrdata[17:16] datatofpgax[3:0] data: mrdata[15:0] datatofpga[31:0] fclk * mr_aemptyn i master read data fifo almost empty. this active-low signal indicates that only four more 64-bit data locations are available to be read from the master read data fifo. fclk * mr_emptyn i master read data fifo empty. this active-low signal indicates that the mas- ter read data fifo is empty. mrdataenn should never be asserted when mr_emptyn is active. fclk * mrlastcycn i master read last data cycle. this active-low signal is asserted to indicate that the accompanying master read data is the nal data word for this opera- tion. mrdataenn must be asserted to receive mrlastcycn . fclk * * the source of the clock ( fclk1 or fclk2 ) for the fifo interface (master or target) is selected in the fpsc con guration manager. pci bus core detailed description (continued) ta b le 6. embedded core/fpga interface signals (continued)
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 22 lucent technologies inc. lattice semiconductor symbol i/o description clock domain master read data fifo signals (continued) mr_stopburstn o stop burst reads. this active-low signal is used by the fpga application to terminate master reads before the read burst length is reached. the master m ust be transferring data on the pci bus for this signal to be effective, and it is recommended to hold this signal until ma_fulln is deasserted. once asserted, this signal needs to remain asserted for a minimum of two pciclk cycles. pciclk ta rg et general t foclrn o ta rg et fifo clear . this active-low signal is asynchronously asserted by the fpga application to clear the target address, read, and write data fifos, along with tstatecntr . this signal does not reset the target controller?s pci state machine, and it is not recommended to be used to terminate the current pci transaction. ? t_ready i ta rg et logic ready. this active-high signal indicates that the target fifo interface to the fpga application is ready. this signal will be inactive during pci bus resets, target fifo clears, and up to 16 clocks after device con gura- tion. this signal can be ignored when transferring data from the target write data fifo, if pci_rstn is inactive. fclk * tstatecntr[3:0] i ta rg et state counter. indicates the current state of the target fifo interface. details of the target fifo interface can be found in the pci bus core target controller detailed description section of this data sheet. fclk * disctimerexpn i discard timer expired. this active-low signal indicates that the discard timer has expired and the target controller has deleted the current transaction which was stored as a delayed transaction. the fpga application should discontinue processing of the current target transaction. the discard timer is a 15-bit counter which starts its count when the target transaction is stored. fclk * t_abort o ta rg et abort. this signal is asserted by the fpga application to abort future pci target and con guration cycles. once asserted, this signal needs to remain asserted for a minimum of two pciclk cycles. pciclk t_retryn o ta rg et retry. this active-low signal is asserted by an fpga application to retry future pci target and con guration cycles. once asserted, this signal needs to remain asserted for a minimum of two pciclk cycles. pciclk deltrn o target read delayed transaction . active-low signal which indicates to pro- cesses certain future pci target accesses as delayed transactions. this applies to memory reads, i/o reads, and i/o writes. further description is pro- vided in table 3 for each pci operation. deltrn must be asserted if trburst- pendn is deasserted. once asserted, this signal needs to remain asserted for a minimum of two pciclk cycles and should not be changed while a current tar- get transaction is in progress. pciclk pci bus core detailed description (continued) ta b le 6. embedded core/fpga interface signals (continued) * the source of the clock ( fclk1 or fclk2 ) for the fifo interface (master or target) is selected in the fpsc con guration manager.
lucent technologies inc. 23 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor ta rg et fifo address and command register control signals treqn i ta rg et request from pci. the target asserts treqn as an indication to the fpga application that a pci target operation has been decoded and is pend- ing. treqn signal will continue to be active until all data has been transferred between the fpga application and the target fifo interface. the fpga appli- cation should use treqn to qualify valid data on following buses: tcmd , bar , twdata (quad-port mode), and datatofpga/datatofpgax (dual-port mode) fclk * taenn o ta rg et address output enable. this active-low signal enables the pci start address to be transferred from the target address fifo to the fpga applica- tion, on either bus twdata (quad-port mode) or datatofpga (dual-port mode, f o_sel = 1). treqn will be asserted to indicate a valid pci target address e xists. fclk * tcmd[3:0] i ta rg et command code. this bus provides the pci command code for a pending target operation, and is valid when treqn is asserted active-low. ? bar[2:0] i base address register number . this bus indicates which of the six bars decoded the pci address for the current target operation, and is valid when treqn is active-low. for 64-bit addresses, the bars pairs will be indicated by n umbers 0, 2, and 4. ? ta rg et write data fifo signals twdataenn o ta rg et write fifo data enable. this active-low signal enables data from the t arget write data fifo onto bus twdata (quad-port mode) or datatofpga (dual- port mode, f o_sel = 1). twdataenn should not be asserted whenever the tar- get write data fifo is empty ( tw_emptyn = 0). fclk * twdata[17:0] (quad-port mode) or datatofpgax[3:0] , datatofpga[31:0] (dual-port mode) i depending on the or3tp12 con guration, only one of these buses will be av ailable to the fpga application. for target operations, these buses will carry the same information, but in different sizes and bit lanes as summarized below: quad-p or t mode dual-p or t mode ( f o_sel = 1) a. target start address: 32- or 64-bit pci start address. address: twdata[15:0] datatofpga[31:0] dual-address indication: twdata[16] datatofpgax[0] burst indication: twdata[17] datatofpgax[1] unused: datatofpgax[3:2] b. target write data: write data from pci bus. data: twdata[15:0] datatofpga[31:0] write enables: twdata[17:16] datatofpgax[3:0] fclk * tw_aemptyn i ta rg et write fifo almost empty. this active-low signal indicates that only f our more 64-bit data locations are available to be read from the target write data fifo. fclk * tw_emptyn i ta rg et write fifo empty. this active-low signal indicates that the target write fifo is empty. twdataenn should never be asserted if tw_emptyn is asserted. fclk * * the source of the clock ( fclk1 or fclk2 ) for the fifo interface (master or target) is selected in the fpsc con guration manager. pci bus core detailed description (continued) ta b le 6. embedded core/fpga interface signals (continued)
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 24 lucent technologies inc. lattice semiconductor symbol i/o description clock domain ta rg et write data fifo signals (continued) twlastcycn i ta rg et write last data cycle. this active-low signal has two functions: a. indicates that the current target start address data on twdata (quad-port) or datatofpga (dual-port with f o_sel = 1) is the nal transfer of the address phase. taenn is required to be asserted to receive twlastcycn . b. indicates that the current target write data on twdata (quad-port) or datatofpga (dual-port with f o_sel = 1) is the nal transfer of the data phase. for single data transfers, it will be asserted on the only word of the transfer, whereas on bursts, if will be asserted only on the nal word. twdataenn is required to be asserted to receive twlastcycn . fclk * twburstpendn o burst write data control. this active-low signal indicates to the target con- troller that a write transaction should not be disconnected immediately when the target write data fifo is full, but allow up to eight wait-states to be inserted. when desasserted, the target controller will disconnect when the write fifos are full. once asserted, this signal needs to remain asserted for a minimum of two pciclk cycles. pciclk ta rg et read data fifo signals trdataenn o ta rg et read fifo data enable. this active-low signal enables the register- ing of bus trdata (quad-port mode) or datafmfpga (dual-port mode) into the t arget read data fifo. trdataenn should not be asserted when the target read data fifo is full ( tr_fulln = 0). fclk * trdata[17:0] (quad-port mode) or datafmfpga[31:0] , datafmfpgax[3:0] (dual-port mode) o depending on the or3tp12 con guration, only one of these buses will be av ailable to the fpga application. for target operations, these buses will carry the same information, but in different sizes as summarized below: ta rg et read data: read data to the pci bus. data: trdata[15:0] datafmfpga[31:0] unused: trdata[17:16] datafmfpgax[3:0] fclk * tr_afulln i ta rg et read fifo almost full. this active-low signal indicates that the tar- get read data fifo has only four more 64-bit empty locations available. fclk * tr_fulln i ta rg et read fifo full. this active-low signal indicates that the target read data fifo is full and that no more data can be accepted. trdataenn m ust not be asserted when tr_fulln is asserted. fclk * trlastcycn i ta rg et read last data cycle . this active-low signal is asserted to indicate the nal cycle of the read data phase. during read bursts, more than one clock is usually required to transfer a complete data phase; therefore, this signal will be asserted only on the last data word. during a read burst, trlast- c ycn may remain inactive for longer than it is required by the external master, leading to transfer of excess data into the target read data fifo. all e xcess data will be cleared when the external master terminates the transac- tion. trlastcycn will only be active only with an asserted trdataenn . fclk * * the source of the clock ( fclk1 or fclk2 ) for the fifo interface (master or target) is selected in the fpsc con guration manager. pci bus core detailed description (continued) ta b le 6. embedded core/fpga interface signals (continued)
lucent technologies inc. 25 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor symbol i/o description clock domain ta rg et read data fifo signals (continued) trpcihold o ta rg et read pci bus hold . f or read transfers to the pci bus, this signal delays the start of the data transfer (i.e., trdyn assertion). the data transfer will begin when trpcihold is deasserted or the target read data fifo becomes full. once asserted, this signal needs to remain asserted for a min- imum of two pciclk cycles. pciclk trburstpendn o target read burst control. this active-low signal directs the target to insert up to eight wait-states between subsequent read data phases before disconnect. when deasserted, the target will disconnect immediately when the target read data fifo becomes empty. if deltrn is inactive, trburst- pendn must be driven active. once asserted, this signal needs to remain asserted for a minimum of two pciclk cycles. pciclk miscellaneous signals pci_intan o pci interrupt request . this active-low signal is used to generate a pci bus interrupt and is forwarded by the embedded core as intan onto the pci bus. once asserted, this signal needs to remain asserted for a minimum of two pciclk cycles. ? fclk1 fclk2 o o fpga clock 1 and 2 . clocks used by the master and target fifo interface logic. fclk1 and fclk2 need to be activated for use by the master and target in the fpsc con guration manager. in dual-port mode, only one of these clocks may be active, while the other should be tied low. ? pciclk i pci clock . pciclk is a buffered version of clk for use by the fpga applica- tion as the main clock, or for control signals which are in the pciclk domain (such as t_retryn , mr_stopburstn , etc.). the fpga may route pciclk to any of the fpga resources, fclk1 or fclk2 , programmable clock managers, etc. ? pci_rstn i pci reset . this active-low signal indicates that a pci bus reset was received from the pci bus ( r stn ). ? fpga_syserror o system error . this pin is used by the fpga to generate a system error on the pci bus. this is passed to the pci bus as serrn . once asserted, this sig- nal needs to remain asserted for a minimum of two pciclk cycles. pciclk * the source of the clock ( fclk1 or fclk2 ) for the fifo interface (master or target) is selected in the fpsc con guration manager. pci bus core detailed description (continued) ta b le 6. embedded core/fpga interface signals (continued)
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 26 lucent technologies inc. lattice semiconductor symbol i/o description clock domain miscellaneous signals (continued) cfgshiftenn pci_cfg_stat o i pci error status control cfgshiftenn is an active-low signal that muxes the output of the pci device status register (pci speci cation 2.1: section 6.2.3) onto signal pci_cfg_stat : cfgshiftenn = 1: pci_cfg_stat outputs the wired-or of all status bits below, after being masked by options in the fpsc con guration manager. cfgshiftenn = 0: pci_cfg_stat outputs each status bit below, shifted one at a time on successive pciclk rising edges. the shift register is reset when cfgshiftenn = 1. device status register bits: detected parity error, signaled system error, received master abort, received target abort, signaled target abort, master data parity error. pciclk pci_64bit i pci 64-bit bus indication. this active-high signal indicates that the embed- ded core detected that it is con gured as a 64-bit agent on the pci bus. this is the result of detecting pci signal req64n as active-low on the rising edge of pci signal rstn . note that this does not imply that any particular transac- tion is 64-bit, since each transaction is individually negotiated using pci sig- nals req64n and ack64n . when asserted, all data transfers across the master and target fifo interface will imply 64-bit data phases. ? f o_sel o fifo select. a mux control signal that is valid in the dual-port mode to select either master read data ( f o_sel = 0) or target address/write data ( f o_sel = 1) on the datatofpga and datatofpgax bu s. f or quad-port mode, this signal can be tied to high. ? pci bus core detailed description (continued) ta b le 6. embedded core/fpga interface signals (continued) * the source of the clock ( fclk1 or fclk2 ) for the fifo interface (master or target) is selected in the fpsc con guration manager.
lucent technologies inc. 27 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core detailed description (continued) embedded core/fpga interface signal locations ta b le 7 lists the physical locations of all signals on the embedded core/fpga interface. separate names are pro- vided for dual-port and quad-port bus signals, since their functionality is port mode dependent. ta b le 7. or3tp12 fpga/pci core interface signal locations embedded core/fpga interface site fpga input signal fpga output signal dual-port mode quad-port mode dual-port mode quad-port mode pb1a disctimerexpn cfgshiftenn pb1b t_ready twburstpendn pb1c pci_cfg_stat (unused) pb1d treqn (unused) pb2a datatofpga0 twdata0 datafmfpga0 trdata0 pb2b datatofpga1 twdata1 datafmfpga1 trdata1 pb2c datatofpga2 twdata2 datafmfpga2 trdata2 pb2d datatofpga3 twdata3 datafmfpga3 trdata3 pb3a datatofpga4 twdata4 datafmfpga4 trdata4 pb3b datatofpga5 twdata5 datafmfpga5 trdata5 pb3c datatofpga6 twdata6 datafmfpga6 trdata6 pb3d datatofpga7 twdata7 datafmfpga7 trdata7 pb4a datatofpga8 twdata8 datafmfpga8 trdata8 pb4b datatofpga9 twdata9 datafmfpga9 trdata9 pb4c datatofpga10 twdata10 datafmfpga10 trdata10 pb4d datatofpga11 twdata11 datafmfpga11 trdata11 pb5a datatofpga12 twdata12 datafmfpga12 trdata12 pb5b datatofpga13 twdata13 datafmfpga13 trdata13 pb5c datatofpga14 twdata14 datafmfpga14 trdata14 pb5d datatofpga15 twdata15 datafmfpga15 trdata15 cktoasb5 (unused) fclk2 pb6a datatofpgax 0 twdata 16 datafmfpgax 0 trdata 16 pb6b datatofpgax 1 twdata 17 datafmfpgax 1 trdata 17 pb6c twlastcycn twdataenn pb6d trlastcycn trdataenn pb7a bar 0 fpga_syserror pb7b bar 1 t_abort pb7c bar 2 t_retryn pb7d pciclk taenn pb8a tstatecntr 0 (unused) pb8b tstatecntr 1 (unused) pb8c tstatecntr 2 (unused) pb8d tstatecntr 3 (unused)
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 28 lucent technologies inc. lattice semiconductor pci bus core detailed description (continued) ta b le 7. or3tp12 fpga/pci core interface signal locations (continued) embedded core/fpga interface site fpga input signal fpga output signal dual-port mode quad-port mode dual-port mode quad-port mode pb9a tw_emptyn trburstpendn pb9b tw_aemptyn t foclrn pb9c tr_fulln trpcihold pb9d tr_afulln pci_intan pb10a tcmd0 mr_stopburstn pb10b tcmd1 m foclrn pb10c tcmd2 mwpcihold pb10d tcmd3 mwlastcycn pb11a ma_fulln (unused) pb11b fpga_msyserror (unused) pb11c mrlastcycn (unused) pb11d m_ready (unused) pb12a mw_fulln maenn pb12b mw_afulln f o_sel pb12c mr_emptyn fpga_mbusyn pb12d mr_aemptynmrdata deltrn pb13a pci_rstn mrdataenn pb13b pci_64bit mwdataenn pb13c datatofpgax2 mrdata16 datafmfpgax2 mwdata16 pb13d datatofpgax3 mrdata17 datafmfpgax3 mwdata17 cktoasb13 (unused) fclk1 pb14a datatofpga16 mrdata0 datafmfpga16 mwdata0 pb14b datatofpga17 mrdata1 datafmfpga17 mwdata1 pb14c datatofpga18 mrdata2 datafmfpga18 mwdata2 pb14d datatofpga19 mrdata3 datafmfpga19 mwdata3 pb15a datatofpga20 mrdata4 datafmfpga20 mwdata4 pb15b datatofpga21 mrdata5 datafmfpga21 mwdata5 pb15c datatofpga22 mrdata6 datafmfpga22 mwdata6 pb15d datatofpga23 mrdata7 datafmfpga23 mwdata7 pb16a datatofpga24 mrdata8 datafmfpga24 mwdata8 pb16b datatofpga25 mrdata9 datafmfpga25 mwdata9 pb16c datatofpga26 mrdata10 datafmfpga26 mwdata10 pb16d datatofpga27 mrdata11 datafmfpga27 mwdata11 pb17a datatofpga28 mrdata12 datafmfpga28 mwdata12 pb17b datatofpga29 mrdata13 datafmfpga29 mwdata13 pb17c datatofpga30 mrdata14 datafmfpga30 mwdata14 pb17d datatofpga31 mrdata15 datafmfpga31 mwdata15 pb18a mstatecntr0 (unused) pb18b mstatecntr1 (unused) pb18c mstatecntr2 (unused) pb18d mstatecntr3 (unused)
lucent technologies inc. 29 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core detailed description (continued) embedded core con guration options ta b le 8 lists all options in the embedded core that can be selected via the fpsc con guration manager. the table also lists the settings available for each option, which is accessible using the fpsc design kit software. ta b le 8. pci bus core options settable via fpga con guration ram bits description hex address in pci con guration space optional settings revision id 0x08 any 8-bit value. class code 0x09?0x0b any 24-bit value. bus master support 0x4: bit 2 three options: t arget only: powerup value: 0; access type: read-only master/target: powerup value: 0; access type: read/write master: powerup value: 1; access type: read- only data parity error detected 0x4: bit 8 mask value for wire-or output pci_cfg_stat . t arget abort signal 0x4: bit 11 mask value for wire-or output pci_cfg_stat. t arget abort received 0x4: bit 12 mask value for wire-or output pci_cfg_stat. master abort received 0x4: bit 13 mask value for wire-or output pci_cfg_stat . system error signaled 0x4: bit 14 mask value for wire-or output pci_cfg_stat . pa r ity error detected 0x4: bit 15 mask value for wire-or output pci_cfg_stat . latency timer initial value 0x0d any 8-bit value divisible by eight (xxxxx000). base address register (bar0/1) area 1 0x10?0x17 refer to pci speci cation 2.2, section 6.2.5.1 up to two 32-bit bars, one 64-bit bar, or none (i.e., unprogrammed). 32-bit bars can target memory or i/o space. memory can be prefetchable or nonprefetchable. if 64-bit bar, must be memory; page size can be from 2 4 bytes to 2 64 bytes. if 32-bit i/o bar, page size can be from 2 2 bytes to 2 32 bytes. if 32-bit memory bar, address space can be 2 4 b ytes to the maximum (2 20 bytes or 2 32 bytes). base address register (bar2/3) area 2 0x18?0x1f same as for bar area 1. base address register (bar4/5) area 3 0x20?0x27 same as for bar area 1.
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 30 lucent technologies inc. lattice semiconductor subsystem vendor id 0x2c?0x2d any 16-bit value. subsystem id 0x2e?0x2f any 16-bit value. minimum grant (min_gnt) 0x3e any 8-bit value. maximum latency (max_lat) 0x3f any 8-bit value. po rt mode dual-port or quad-port. i/o mode fast or slew-limited pci output buffers. master fifo interface clock fclk1 or fclk2 . t arget fifo interface clock fclk1 or fclk2 . t arget address comparator enabled or disabled; when enabled, the target fifo interface will not transfer the msb of the target address to the fpga application, if it matches the v alue of the previous transferred address. for dual- port, the msb will cover bits [64:32], whereas for quad-port, the msb represents bits [64:17]. if dis- abled, the fpga application will receive the address covering the decoded bar space. t arget maximum initial latency normal (16) or extended (32): the number of wait- states to insert on target reads until valid data is recognized in the target read data fifos. if no data is detected, the target will disconnect. note that only normal initial latency complies with pci speci - cation 2.2, section 3.5.1.1. extended latency may be speci ed in proprietary systems where additional clocks are required to return the rst data word. description hex address in pci con guration space optional settings pci bus core detailed description (continued) ta b le 8. pci bus core options settable via fpga con guration ram bits (continued)
lucent technologies inc. 31 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core detailed description (continued) embedded core/fpga fifo interface operation summary the following sections describe the master and target fifo interface operation between the pci bus core and the fpga application. table 9 is an index to the state tables and timing gures provided for each of the operational modes (dual-port, quad-port) of the fifo interface. ta b le 9. index to state sequence tables * the fpga interface does not participate in target con guration operations. dual-port mode quad-port mode master/ target pci access t ype address t ype single/burst and delayed/ nondelayed pci bus timing figure state table fpga bus timing figure state table fpga bus timing figure master write con g, memory, i/o single 5 13 3 14 4 burst 8 6 7 read con g, memory, i/o single 11 15 9 16 17 10 burst 14 12 13 t arget write con g single 15 20 * 21 * i/o single, delayed ? 18 19 single, nondelayed 16 memory single 17 burst 20 21 22 read con g single 23 22 * 23 * i/o delayed 24 27 28 nondelayed 25 memory single 29 single, delayed 26 burst 33 31 32 burst, delayed 30
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 32 lucent technologies inc. lattice semiconductor pci bus core master controller detailed description fifo interface overview the master fifo interface consists of two transfer phases: command/address followed by data. this sequence must be followed, with the assertion of mwlastcycn indicating the completion of each phase. in both quad- and dual-port modes, the command is transferred rst, followed by address, then data. the pci start address and bus command are always pro- vided by the fpga application. for master writes, write data with byte enables will be provided by the fpga application, whereas for reads the master will receive its data from the pci bus and forward on to the fpga application. all types of data are transferred on the data paths de ned by the operational mode (dual- or quad- port). master state counter the master fifo interface provides a state counter, mstatecntr[3:0] , that informs the fpga application of its current state (table 12). this state counter deter- mines what data is expected from the fpga applica- tion during the command/address or write data phases, or what is currently being provided by the master fifo interface during read data phases. this state counter transitions from one state to another in a predeter- mined manner. table 13 through table 17 detail the sequencing of the mstatecntr and the data transferred f or master write and read transactions. the value on bus mstatecntr can be used to minimize fpga logic or verify proper operation. the data pro- vided by the master fifo interface to the fpga appli- cation is accompanied by a value on mstatecntr[3:0] , as shown in table 12. this value can be directly used by the fpga application to determine the proper orien- tation of the master read data. this eliminates the need f or logic in the fpga application for possible data pack- ing functions. the data required from the fpga appli- cation by the master fifo interface during the command/address or write data is also de ned by the v alue on mstatecntr . however, the state counter value being presented to the fpga application is in the same cycle that the data is sent from the fpga. here, the v alue provided by the master fifo interface can be used to determine the next state, since current data, phase, enables, and state transitions is known. dual-master address holding registers the master fifo interface utilizes a pair of 64-bit address holding registers to reduce latency when set- ting up repeated master transfers to or from the same pci address. every master command/address phase has associated with it one of the two holding registers, as speci ed by the holding register selector (master command word bit 12, as described in table 10). each address holding register records the full previous address, allowing some, all, or none of that recorded address to be used to build the next address associ- ated with that holding register. this can save up to 2/4 cycles (for dual-port/quad-port mode, respectively) dur- ing the command/address phase. the holding register supplies the most signi cant por- tion, or all, or none, of the address. the amount sup- plied by the holding register is determined by the timing of the signal mwlastcycn , which accompanies the last portion of data during the command/address phase. if mwlastcycn accompanies the master command word, the holding register supplies the entire address. table 11 gives examples of typical operation using the hold- ing registers, illustrating the above rules. the holding registers can be partitioned using one each for read and write operations, thus providing two unrelated addresses for two functions. another useful application is to dedicate one holding register to a x ed address such as the beginning of a buffer, the data port of a fifo or a mailbox register. this increases effective bandwidth on shorter bursts.
lucent technologies inc. 33 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core master controller detailed description (continued) ta b le 10. bit de nitions for master command/address phase * refer to pci speci cation 2.3 section 3.1. master write operation command/address setup in order to initiate a pci master write operation, the fpga application must supply the master command and pci start address in the speci c order prescribed in table 13 and table 14, for quad- and dual-port mode respectively. this data is transferred via bus mwdata (quad-port mode) or datafmfpga ( x ) (dual-port mode) and will be accepted by the master fifo interface when ma_fulln is inactive and m_ready is active. the master command word and address must be accompanied by assertion of the enable maenn , with the command/address phase ending with the assertion of mwlastcycn . the bit de nitions of the master command word is shown in table 10. for master writes, the same burst length bit must be equal to zero. all burst transactions or 64-bit agents ( pci_64bit = 1) must start transactions on a 64-bit address boundary, which requires address bit ad2 = 0 for the pci start address. if the write transaction needs to start on a odd 32-bit address boundary ( ad2 = 1), the fpga must send a padding data word to properly ll/align the master write data fifo at the beginning of the data phase. this padding data word will be the rst write data word transferred from the fpga application, and will have all of its byte enables deasserted. when the master starts the pci transaction on a 32-bit bus, this padding data word will be dropped by the master, with the resulting transaction starting on the odd address ( ad2 = 1). f or single 32-bit transaction on 32-bit buses ( pci_64bit = 0), the master fifo interface will perform the proper data alignment. the fpga application will transfer the pci starting address, even or odd, during the command/address phase and the valid 32-bit data word during the data phase. bits name description quad-port dual-port master command word (fpga pci core) 17 spl master read: same previous burst length indication (quad-port only) master write: must be zero mwdata[17] datafmfpgax[3] 16 da dual-address indication mwdata[16] datafmfpgax[2] 15:13 ? not used mwdata[15:13] datafmfpga[31:29] 12 hr holding register selector: 0 = select hr0 1 = select hr1 mwdata[12] datafmfpga[28] 11:4 mrdben master read: byte enables master write: not used mwdata[11:4] datafmfpga[27:20] 3:0 cmd pci command code* mwdata[3:0] datafmfpga[19:16] master read burst length word (fpga pci core) 17:16 bl burst length of 64-bit words mwdata[17:16] datafmfpgax[1:0] 15:0 bl burst length of 64-bit words mwdata[15:0] datafmfpga[15:0] master address word (fpga pci core) 17:16 ? not used mwdata[17:16] datafmfpgax[1:0] 15:0 adrs address mwdata[15:0] datafmfpga[31:0]
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 34 lucent technologies inc. lattice semiconductor pci bus core master controller detailed description (continued) ta b le 11. holding registers, examples of typical operation ta b le 12. master state counter (mstatecntr) values and the corresponding bus data * same burst length speci ed in bit 17 of command word for master reads, or master write operation. address transfer on bus mwdata mwlastcycn v alid with: hold- ing reg. select holding register 0 initial value holding register 1 initial value master start address a3 a2 a1 a0 a3 a2 a1 a0 a3 a2 a1 a0 a3 a2 a1 a0 1111 1111 1111 1111 a3 0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 1111 1111 1111 1111 ?? ? 2222 a0 0 1111 1111 1111 1111 xxxx xxxx xxxx xxxx 1111 1111 1111 2222 0123 4567 89ab cdef a3 1 1111 1111 1111 2222 xxxx xxxx xxxx xxxx 0123 4567 89ab cdef ?? ?? cmd 0 1111 1111 1111 2222 0123 4567 89ab cdef 1111 1111 1111 2222 ?? 3333 4444 a1 0 1111 1111 1111 2222 0123 4567 89ab cdef 1111 1111 3333 4444 ? 5555 6666 7777 a2 0 1111 1111 3333 4444 0123 4567 89ab cdef 1111 5555 6666 7777 8888 9999 aaaa bbbb a3 0 1111 5555 6666 7777 0123 4567 89ab cdef 8888 9999 aaaa bbbb ?? ?? cmd 1 8888 9999 aaaa bbbb 0123 4567 89ab cdef 0123 4567 89ab cdef cccc dddd eeee ffff a3 1 8888 9999 aaaa bbbb 0123 4567 89ab cdef cccc dddd eeee ffff ?? ?? cmd 0 8888 9999 aaaa bbbb cccc dddd eeee ffff 8888 9999 aaaa bbbb mstatecntr[3:0} dual-port mode (32-bit ports) quad-port mode (16-bit ports) mstatecntr[3:0] data on bus datafmfpga data on bus datatofpga data on bus mwdata data on bus mrdata 0 burstlength, command word read data [31:0] command word read data [15:0] 1 adrs[31:0] read data [63:32] burstlength adrs[15:0]* read data [31:16] 2 adrs[63:32] ? adrs[15:0] adrs[31:16]* read data [47:32] 3? ? adrs[31:16] adrs[47:32]* read data [63:48] 4? ? adrs[47:32] adrs[63:48]* ? 5? ? adrs[63:48] ? 6? ?w r ite data [15:0] ? 7? ?w r ite data [31:16] ? 8? ?w r ite data [47:32] ? 9? ?w r ite data [63:48] ? aw r ite data [31:0] ? ? ? bw r ite data [63:32] ? ? ?
lucent technologies inc. 35 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core master controller detailed description (continued) write data phase the fpga application begins the write data phase by deasserting maenn and asserting mwdataenn . on ev ery clock cycle that mwdataenn is asserted, the fpga application will transfer write data and its associ- ated byte enables into the master write data fifo (sixty-four 32-bit words; thirty-two 64-bit words) via bus mwdata (quad- port mode) or datafmfpga (dual-port mode). mwdataenn must not be asserted when the write data fifos are full ( mw_fulln is asserted). note that mw_fulln can be updated on the same clock edge as mwdataenn is sampled. the distinction between a burst write and a single access is provide by the mwlastcycn signal instead of using a burst length. this allows the fpga application to maintain control over the length of the master write b urst. when mwlastcycn is asserted, this informs the master fifo interface of the end of the write data phase. mwlastcycn will be deasserted for every data element except the last element on bus mwdata (quad- port mode) or datafmfpga (dual-port mode). mwlast- c ycn can remain asserted throughout a single (non- b urst) master write. for example, to perform a single 32-bit word transfer in dual-port mode, mwlastcycn w ould be asserted during the entire data phase, since the last data phase is the only data phase. note if mwlastcycn is asserted, mwdataenn must be asserted. when executing a burst master write or on a 64-bit bus ( pci_64bit = 1), the write data transferred from the fpga application is aligned on 64-bit address bound- aries, which may require padding of write data to prop- erly ll/align the write data fifos. for transfers starting at an odd 32-bit pci address ( ad2 = 1), this will require a 32-bit padding data word at the beginning of the write data phase. padding of fifo is accomplished by trans- f erring a data word with its byte enables deasserted. in 64-bit transfers, the padding word will be place on the a 32-bit segment with its byte enables deasserted and the external target will ignore it. for 32-bit wide data transfers, this padding word will be ignored and not transferred to the pci bus. f or single 32-bit transaction on 32-bit buses ( pci_64bit = 0), the master fifo interface will perform the proper data alignment. the fpga application only needs to transfer the valid 32-bit data word during the data phase. fifo full/almost full when the master write data fifo contains four or fe w er 64-bit empty locations, the master fifo interface asserts mw_afulln , the almost full indicator. this allows some latency to exist in the fpga?s response without risking over lling the fifo. when all locations in the master write data fifo are full, the master fifo interface asserts mw_fulln , the fifo full indicator. since data can be simultaneously written to and read from the master write fifo, both mw_afulln and mw_fulln can change states in either direction multiple times in the course of a burst transfer. master write hold the signal mwpcihold can be asserted to delay the initiation of a master write operation, i.e., reqn asserted, until an greater amount of data is available in the write data fifos. normally, the master write opera- tion would begin after the rst write data word is received by the master fifo interface. while mwpci- hold is active, write data can be transferred from the fpga application into the write fifos. when the mas- ter write fifos become full or mwpcihold is deas- serted, the master write operation will begin on the pci b us ( reqn asserted). mwpcihold must be deasserted at least two pciclks before mwlastcycn is asserted, which indicates the end of the write data phase. use of this signal can result in more ef cient utilization of pci bus bandwidth by causing a full buffer contents to be bursted, without wait-states, after the pci bus is claimed. w ait-states the master will not insert wait-states into a write trans- fe r, as long as the master write data fifo is nonempty. if the master write data fifo becomes empty before mwlastcycn was asserted by the fpga application, w ait-states will be inserted until more write data is pro- vided or the external target disconnects. if the fpga application cannot provide subsequent data to the master write data fifo within an eight pciclk period, it is recommended to end the data phase by asserting mwlastcycn and mwdataenn , along with a valid data w ord, to avoid excessive wait-states insertion.
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 36 lucent technologies inc. lattice semiconductor pci bus core master controller detailed description (continued) t ermination once initiated, master write operations will continue on the pci bus until either all write data is sent, an abort occurs (either master or target), or the pci bus? reset signal ( r stn ) is asserted. during aborts, the master address and write data fifos will be cleared, and the fpga application will be noti ed by the assertion of fpga_msyserror . if the master write transaction is terminated with a retry or disconnected by the external target before all data has been transferred, the master will initiate another master write operation, continuing from that point using a stored address pointer. on the master fifo interface, the fpga application identi es the last data word by asserting mwlastcycn . when this data word is transferred to the pci bus, the master will terminate the pci transaction normally. the master will inform the fpga application of completion by deasserting ma_fulln . reset the fpga application can apply a reset signal to place the master fifo interface logic in a known state, which clears all fifos and mstatecntr . the reset signal, m foclrn , is asynchronous and therefore should be asserted for a minimum of one clock cycle and deas- serted for a minimum of one clock cycle before continu- ing. this is not recommended to assert m foclrn while a current pci transaction is in progress ( ma_fulln asserted), since proper pci bus termination is not guaranteed. only pci r stn will reset the internal master pci state machines, while a pci transaction is in progress.
lucent technologies inc. 37 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core master controller detailed description (continued) example: master write, single-word transaction figure 3 and figure 4 shows the timing of a master write, single 32-bit data word, on the dual-port fpga interface and quad-port fpga interface, respectively. in figure 3, the command/address phase is initiated by the fpga application asserting master address enable ( maenn ), while providing the master command word on bus datafmf- pga . on the next clock, the fpga application provides the 32-bit address and ends the command/address phase by asserting mwlastcycn for the write data phase. to enter the data phase, maenn is deasserted, mwdataenn is asserted, and a valid 32-bit dword of data provided on bus datafmfpga . f or a 32-bit transfer on a 32-bit pci bus ( pci_64bit = 0), the fpga application asserts the sig- nal mwlastcycn during the only clock of the data phase. after the rst write data word is provided, ma_fulln goes active indicating the master will be begin negotiating for the pci bus. f or quad-port mode (figure 4), the command/address and write data is transferred on the bus mwdata in 16-bit segments. the 18-bit master command will remain unchanged, but the 32-bit address will be split into two 16-bit components with the lsb being transferred rst. the command/address phase will require three clock cycles ( maenn asserted), and mwlastcycn will be asserted on the nal or msb component of the address. the data phase will also require additional clock cycles to transfer the 32-bit write data word across the bus mwdata . similar to above, the data phase will be entered with the deassertion of maenn and assertion of mwda- taenn . mwlastcycn will be deasserted for the initial 16-bit lsb of the write data word and asserted for the nal 16-bit msb component. in figure 5, execution begins on the pci bus which shows the timing of a transaction with an external target. the transaction results in a normal completion. it is a typical pci transaction with a remote target that supports fast decode, and the protocol and timing are as required by the pci speci cation. 5-7350(f) figure 3. master write single (fifo interface, dual-port) t0 t1 t2 t3 t4 t5 0 1 a 0 cmd adrs d0 fclk m_ready mstatecntr ma_fulln datafmfpga maenn mw_fulln mwdataenn mwlastcycn
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 38 lucent technologies inc. lattice semiconductor pci bus core master controller detailed description (continued) 5-7358(f) figure 4. master write single (fifo interface, quad-port) 5-7366(f) figure 5. master write single (pci bus, 32-bit) t0 t1 t2 t3 t4 t5 t6 t7 tn 0 1 2 6 7 0 cmd adrs0 adrs1 d0 fclk m_ready nstatecntr ma_fulln mwdata maenn mw_fulln mwdataenn mwlastcycn d1 t0 t1 t2 t3 t4 adrs data cmd byte enables clk framen ad c_ben irdyn devseln trdyn stopn
lucent technologies inc. 39 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core master controller detailed description (continued) example: master write, burst transaction figure 6 and figure 7 show the timing of a master write of four 32-bit data words, on the dual-port fpga interface and quad-port fpga interface, respectively. in figure 6, the command/address phase is initiated by the fpga application asserting master address enable ( maenn ), while providing the master command word on bus datafm- fpga . on the next clock, the fpga application provides the 32-bit address and ends the command/address phase by asserting mwlastcycn . to enter the data phase, maenn is deasserted, mwdataenn is asserted, and a valid 32-bit dword of data provided on bus datafmfpga . after the second write data word is provided, ma_fulln goes active indicating the master will be begin negotiating for the pci bus (assuming mwpcihold is deaserted). the fpga application continues to sup- ply data (three 32-bit dwords) on bus datafmfpga with mwdataenn asserted, while monitoring the mw_fulln ag. to indicate the completion of the data phase, mwlastcycn is asserted, along with mwdataenn , during the nal data word. f or quad-port mode (figure 7), the command/address and write data is transferred on the bus mwdata . the 18-bit master command will remain unchanged, but the 32-bit address will be split into two 16-bit components with the lsb being transferred rst. the command/address phase will require three clock cycles (with maenn asserted), and mwlastcycn will be asserted on the nal or msb component of the address. the quad-port data phase will also require additional clock cycles to transfer the four 32-bit write data word across the bus mwdata . similar to above, the data phase will be entered with the deassertion of maenn and assertion of mwdataenn . mwlastcycn will be deasserted for all write data words, except being asserted for the nal 16-bit msb component. execution begins on the pci bus, as shown in figure 8, which shows the timing with an external target. the trans- action runs to normal completion. it is a typical pci transaction (the remote target supports fast decode), and the protocol and timing are as required by the pci speci cation. 5-7351(f) figure 6. master write burst (fifo interface, dual-port) t0 t1 t2 t3 t4 t5 t6 t7 t8 0 1 a b a b 0 cmd adrs d0 d1 d2 d3 fclk m_ready mstatecntr ma_fulln datafmfpga maenn mw_fulln mwdataenn mwlastcycn
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 40 lucent technologies inc. lattice semiconductor pci bus core master controller detailed description (continued) 5-7359(f) figure 7. master write burst (fifo interface, quad-port) 5-7367(f) figure 8. master write burst (pci bus, 32-bit) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 0 1 2 6 7 8 9 6 7 8 0 d0 d2 d3 d4 d5 d6 d7 fclk m_ready mstatecntr ma_fulln mwdata maenn mw_fulln mwdataenn mwlastcycn d1 cmd adrs0 adrs1 9 t0 t1 t2 t3 t4 t5 t6 adrs d0 d1 d2 d3 cmd be0 be1 be2 be3 clk framen ad c_ben irdyn devseln trdyn stopn
lucent technologies inc. 41 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core master controller detailed description (continued) ta b le 13. dual-port master writes 1. when maenn and ma_fulln are deasserted high, the master interface is idle. 2. when maenn is asserted low, a command/address phase is in progress. 3. maenn must be asserted low for command/address data to transfer and state to change. 4. maenn must be deasserted high and mwdataenn must be asserted low to execute the data phase and state to change. 5. next state = 0 if mwlastcycn is asserted low (end of master write data phase). 6. next state = a if mwlastcycn is asserted low (end of master command/address phase). ta b le 14. quad-port master writes 1. when maenn and ma_fulln are deasserted high, the master interface is idle. 2. when maenn is asserted low, a command/address phase is in progress. 3. maenn must be asserted low for command/address data to transfer and state to change. 4. maenn must be deasserted high and mwdataenn must be asserted low to execute the data phase and state to change. 5. next state = 0 if mwlastcycn is asserted low (end of master write data phase). 6. next state = 6 if mwlastcycn is asserted low (end of master command/address phase). mstatecntr next state of mstatecntr description data on bus datafmfpgax[3:0], datafmfpga[31:0] notes 00 idle xxxx 4 , xxxx 16 1 01 or a command word command word [17:16], xx 2 , command word [15:0], xxxx 16 2, 3, 6 12 or a address[31:0] xxxx 4 , pciaddress[31:0] 2, 3, 6 2a address[63:32] xxxx 4 , pciaddress[63:32] 2, 3, 6 ab or 0 data[31:0] ben[3:0], pcidata[31:0] 4, 5 ba or 0 data[63:32] ben[7:4], pcidata[63:32] 4, 5 mstatecntr next state of mstatecntr description data on bus mwdata[17:0] notes 00 idle xx 2 , xxxx 16 1 01 or 6 command word command word 2, 3, 6 12 or 6 address[15:0] xx 2 , pciaddress[15:0] 2, 3, 6 23 or 6 address[31:16] xx 2 , pciaddress[31:16] 2, 3, 6 34 or 6 address[47:32] xx 2 , pciaddress[47:32] 2, 3, 6 46 address[63:48] xx 2 , pciaddress[63:48] 2, 3, 6 67 data[15:0] ben[1:0], pcidata[15:0] 4 78 or 0 data[31:16] ben[3:2], pcidata[31:16] 4, 5 89 data[47:32] ben[5:4], pcidata[47:32] 4 96 or 0 data[63:48] ben[7:6], pcidata[63:48] 4, 5 master read operation command/address setup in order to initiate a pci master read operation, the fpga application must supply the master command, master read burst length, and pci start address in the specific order prescribed in table 15 and table 17, for quad- and dual-port mode respectively. the bit de ni- tions of the master command word are shown in ta b le 10. this data is transferred via bus mwdata (quad-port mode) or datafmfpga (dual-port mode), and cannot be accepted by the master fifo interface unless ma_fulln is inactive and m_ready is active. the master command word, master read burst length, and start address must be accompanied by assertion of the enable maenn , with the command/address phase end- ing with the assertion of mwlastcycn . after the com- mand/address phase completes, ma_fulln goes active indicating the master will be begin negotiating for the pci bus.
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 42 lucent technologies inc. lattice semiconductor pci bus core master controller detailed description (continued) the master uses the read burst count supplied during command/address phase to determine number of 64-bit words the master read operation should transfer (unlike the master write, which uses signal mwlast- c ycn ). if the burst length for a master read operation is the same as for the previous master operation, the fpga application may elect to set bit 17 of the master command word. in this case, no burst length is sup- plied; and the read burst length from the previous oper- ation is used. this saves a clock cycle during the command/address phase when in quad-port mode, but should remain zero for the dual-port mode. all read transactions require an address on a 64-bit boundary, which requires ad2 = 0. the read burst length will indicate the number 64-bit words to retrieve from this address. all burst read transaction may trans- f er twice the read burst length of 32-bit words on a 32-bit pci bus ( pci_64bit = 0). on a 64-bit pci bus ( pci_64bit = 1), the number of transfers may equal the read burst length. all read byte enables in the master command word must be asserted for a burst read transaction. single 32-bit transactions require a burst length of one. f or single 32-bit reads on a 32-bit pci bus ( pci_64bit = 0), the read byte enables mrdben[7:0] can modify the start address. using mrdben[7:0] = xf0 will not modify the start address, whereas mrd- ben[7:0] = x0f will. for example on a 32-bit data bus ( pci_64bit = 0), a read transaction with an even 64-bit starting address and read byte enables of 0x0f will retrieve a 32-bit word at the starting address + 0x4. for the case of read byte enables of 0xf0, the 32-bit word will be retrieved from the starting address. read data phase transfer the fpga application begins the read data phase by deasserting maenn and asserting mrdataenn . on ev ery cycle that mrdataenn is asserted and f o_sel is deasserted, the fpga application will receive read data from the master read fifo (sixty-four 32-bit w ords; thirty-two 64-bit words) via bus mrdata (quad- port mode) or datatofpga (dual-port mode), providing the read data fifos are not empty ( mr_emptyn = 1). no byte enables are collected from the pci bus, and therefore mrdata[17:16] and datatofpgax[3:0] will be unused. mrdataenn must not be asserted when the read data fifos are empty ( mr_emptyn is asserted). note that mr_emptyn can be updated on the same clock edge as mrdataenn is sampled. the distinction between a burst read and a single access is provided by the read burst length count and the master read byte enables. when the read burst is g reater than one, or has all of its read byte enables asserted with pci_64bit = 0, it informs the master of a b urst read data phase for 32-bit pci buses. during b ursts, mrlastcycn will be deasserted for every data element received from the master fifo interface while mrdataenn is asserted ( f o_sel is deasserted), except the last element. for a single 32-bit word transfer in dual-port mode on a 32-bit pci bus ( pci_64bit = 0), mrlastcycn would be asserted during the entire data phase, since the last data phase is the only data phase of this transfer. note that for mrlastcycn to be asserted, mrdataenn must be asserted. when executing a burst master read, or with 64-bit agents ( pci_64bit = 1), the read data transferred to the fpga application is always aligned on 64-bit address boundaries, which may require transfer of extra read data for activity on 32-bit pci buses. for read transfers from an odd 32-bit pci address ( ad2 = 1), this will imply receiving an extra 32-bit read data word from the pci bus at the beginning of the read data phase. for transfers starting at an even pci address ( ad2 = 0) requiring an odd number of 32-bit data words, an extra 32-bit read data word is received at the end. the extra read data can be discarded by the fpga application. f or single 32-bit transactions, on 32-bit buses ( pci_64bit = 0), the master fifo interface will perform the proper data alignment. the fpga application only needs to transfer the valid 32-bit word during the data phase. master read data fifo empty/almost empty when the master read data fifo contains four or fewer 64-bit data elements, the master fifo interface asserts mr_aemptyn , the almost empty indicator. this allows some latency to exist in the fpga?s response without risking overreading the fifo. when all loca- tions in the master read data fifo are empty, the mas- ter fifo interface asserts mr_emptyn , the fifo empty indicator. since data can be simultaneously writ- ten to and read from the master read fifo, both mr_aemptyn and mr_emptyn can change states in either direction multiple times in the course of a burst data transfer.
lucent technologies inc. 43 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core master controller detailed description (continued) master read byte enables during master reads, read byte enables are always supplied by the master to the external target, even though on reads the data is o wing in the opposite direction. thus, the byte enables cannot be buffered in the read data fifo alongside the corresponding data. also, the byte enables must be presented on the bus by the master at the same time that the data is being pre- sented on the bus by the external target (unless the e xternal target uses trdyn to insert wait-states). the data provided by the external target cannot depend on the byte enables unless wait-states are inserted. since the byte enables are not buffered, they are de ned in the master command word (bits [11:4]) and are held static throughout the read transaction. their polarity is active-low assertion. f or burst read transactions, the read byte enables must all be asserted. burst read transactions on a 32-bit agent ( pci_64bit = 0) are de ned with a burst length of one or greater, and the read byte enables mrd- ben[7:0] asserted. mixed read byte enables are not allowed for bursting, but are allowed for single accesses. single accesses for a 32-bit pci bus ( pci_64bit = 0) are de ned with a read burst length of one, and the either of the following combination of read b yte enables: mrdben[7:4] = 0xf or mrdben[3:0] = 0xf. for 64-bit single access ( pci_64bit = 1, read burst length = 1), any combination of the read byte enables is v alid. w ait-states the master will only insert wait-states into a read trans- action when the master read data fifo is full, the burst length count has not been reached, and target is not disconnecting. if the fpga application cannot receive data from the master read data fifos within an eight pciclk period, it is recommended to end the read trans- action by asserting mr_stopburstn and mrdataen , while storing the valid read data word, to avoid exces- sive wait-state insertion. read transaction termination once initiated, master read operations will repeat on the pci bus until all data is received, an abort occurs (either master or target), the pci bus? reset signal ( r stn ) is asserted, or mrstopburstn is asserted. on an abort, the master address fifo is cleared, but the master read data fifo will continue to hold all data received before the abort. the master read data fifo m ust be emptied before starting a new master transac- tion. mrstopburstn can be used by the fpga application to terminate a master read transaction before the read b urst length has been reached. this signal is only effective if the master can receive data from an external t arget ( irdynn and framen asserted). since the fpga application has no visibility of the pci bus control sig- nals, mrstopburstn should be held active until ma_fulln is deasserted. on the master fifo interface, mrlastcycn indicates when the last item of the read transaction is being transferred, although the transaction may have ended earlier. the transaction on the pci bus that has been terminated by master is indicated by ma_fulln being deasserted. if a pci transaction is terminated with a retry or discon- nect before all data has been received, the pci bus core will initiate another master read operation, con- tinuing from that point. master read fifo interface reset the fpga application can apply a reset signal to place the master fifo interface in a known state, which clears all fifos and resets the mstatecntr . the reset signal, m foclrn , is asynchronous and therefore should be asserted for a minimum of one clock cycle and deasserted for a minimum of one clock cycle before continuing. it is not recommended to assert m foclrn while a current pci transaction is in progress ( ma_fulln asserted), since proper pci bus termination is not guaranteed. only r stn will reset the internal mas- ter pci state machines, while a pci transaction is in progress. example: master read, single-word transaction figure 9 and figure 10 show the timing of a master read, single 32-bit data word, on the dual-port fpga interface and quad-port fpga interface, respectively. in figure 9, the command/address phase is initiated by the fpga application asserting master address enable ( maenn ), while providing the master command word and read burst length on bus datafmfpga . assuming the master will decode the supplied burst length of one, 32-bit pci bus width ( pci_64bit = 0), and read byte enable (mrdben[7:0] = 0xf0), this is a single opera- tion. on the next clock, the fpga application provides the 32-bit address and ends the command/address phase by asserting mwlastcycn . ma_fulln then will be asserted, and the master will begin negotiating for the pci bus.
44 44 lucent technologies inc. orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 lattice semiconductor pci bus core master controller detailed description (continued) to enter the dual-port data phase, maenn is deas- serted, mrdataenn is asserted, f o_sel is deasserted, and a valid 32-bit word of data will be provided on bus datatofpga , providing the read data fifo is not empty ( mr_emptyn = 1). for a 32-bit transfer on a 32-bit pci bus ( pci_64bit = 0), the master fifo inter- f ace will assert the signal mrlastcycn during the only clock of the data phase. the completion of the data phase is indicated by mrlastcycn being asserted, requiring mrdataenn asserted, and the nal data word. f or quad-port mode (figure 10), the command/address phase starts with the command and read burst length transferring on the bus mwdata in sequential 18-bit segments. the 18-bit master command will be trans- f erred rst on mwdata , followed the 18-bit read burst length, with both validated by an asserted maenn . the 32-bit address will be split into two 16-bit components with the lsb being transferred rst, also validated by an asserted maenn . the command/address phase will require four clock cycles, and mwlastcycn will be asserted on the nal or msb component of the address. in the data phase of the quad-port mode, the read data will be transferred in 16-bit segments on bus mrdata. the read data phase will require two clock cycles to transfer the 32-bit read data word across the 16-bit bus mrdata , providing mrdataen is asserted, and the read data fifos are not empty ( mr_emptyn = 1). mrlast- c ycn will be deasserted for the rst 16-bit lsb of the read data word, and asserted for the nal 16-bit msb component. f ollowing this command/address setup, execution begins on the pci bus. figure 11 shows the timing of a typical transaction with a remote target. the transac- tion results in a normal completion. the remote target supports fast decode, and the protocol and timing are as required by the pci speci cation. 5-7352(f) figure 9. master read single (fifo interface, dual-port) t0 t1 t2 t3 t4 tn tn+1 tn+2 tn+3 0 1 0 0 brst/cmd adrs data fclk m_ready mstatecntr ma_fulln datafmfpga maenn mwlastcycn datatofpga fifo_sel mr_emptyn mrdataenn mrlastcycn
lucent technologies inc. 45 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core master controller detailed description (continued) 5-7360(f) figure 10. master read single (fifo interface, quad-port) 5-7368(f) figure 11. master read single (pci bus, 32-bit) t0 t1 t2 t3 t4 t5 tn+0 tn+0 tn+1 tn+2 tn+3 tn+4 0 1 2 3 0 1 0 cmd brst adrs0 adrs1 d0 d1 fclk m_ready mstatecntr ma_fulln mwdata maenn mwlastcycn mrdata mr_emptyn mrdatenn mrlastcycn t0 t1 t2 t3 t4 t5 adrs data cmd byte enables clk framen ad c_ben irdyn devseln trdyn stopn
46 46 lucent technologies inc. orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 lattice semiconductor pci bus core master controller detailed description (continued) example: master read, burst transaction figure 12 and figure 13 show the timing of a four 32-bit w ord master burst read, on the dual-port fpga inter- f ace and quad-port fpga interface, respectively. oper- ation is similar to that in the master read, single-word transaction, but extra data dwords are requested by the fpga application. in figure 12, the command/ address phase is initiated by the fpga application asserting master address enable ( maenn ), while pro- viding the master command word and read burst length on bus datafmfpga . assuming, the master will decode a supplied burst length of two, and read byte enable (mrdben[7:0] = 0x00), this is a burst operation. on the next clock, the fpga application provides the 32-bit address and ends the command/address phase by asserting mwlastcycn . ma_fulln then will be asserted, and the master will begin negotiating for the pci bus. to enter the dual-port read data phase, maenn is deasserted, mrdataenn is asserted, and valid 32-bit data words will be provided on bus datatofpga ( f o_sel = 0), providing the read data fifo is not empty ( mr_emptyn = 1). for a burst transfer, the mas- ter fifo interface will assert the signal mrlastcycn during the last clock of the data phase, and deasserted otherwise. the completion of the data phase is indi- cated by mrlastcycn asserted, requiring mrdataenn asserted, and the nal data word. f or quad-port mode (figure 13), the command/address phase starts with the command and read burst length transferring on the bus mwdata in sequential seg- ments. the 18-bit master command will be transferred rst on mwdata , followed the 18-bit read burst length, with both validated by an asserted maenn . the 32-bit address will be split into two 16-bit components with the lsb being transferred rst, also validated by an asserted maenn . the command/address phase will require four clock cycles, and mwlastcycn will be asserted on the nal or msb component of the address. in the read data phase of the quad-port mode, the read data will be transferred in 16-bit segments on bus mrdata . the read data phase will require two clock cycles to transfer each 32-bit read data word across the 16-bit bus mrdata , providing mrdataen is asserted, the read data fifos are not empty ( mr_emptyn = 1). mrlastcycn will be deasserted for the all cycles of the data phase, and asserted for nal the 16-bit msb com- ponent. f ollowing this command/address setup, execution begins on the pci bus. figure 14 shows the timing of a typical transaction with a remote target. the transac- tion results in a normal completion. the remote target supports fast decode, and the protocol and timing are as required by the pci speci cation.
lucent technologies inc. 47 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core master controller detailed description (continued) 5-7353(f) figure 12. master read burst (fifo interface, dual-port) t0 t1 t2 t3 t4 tn tn+1 tn+2 tn+3 tn+4 tn+5 0 1 0 0 1 0 1 0 brst/cmd adrs d0 d1 d2 d3 fclk m_ready mstatecntr ma_fulln datafmfpga maenn mwlastcycn datatofpga fifo_sel mr_emptyn mrdataenn mrlastcycn
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 48 lucent technologies inc. lattice semiconductor pci bus core master controller detailed description (continued) 5-7361(f) figure 13. master read burst (fifo interface, quad-port) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 0 1 2 3 0 1 2 3 0 1 2 3 0 adrs0 adrs1 d0 d1 d2 d3 d4 d5 d6 d7 fclk m_ready mstatecntr ma_fulln mwdata maenn mwlastcycn mrdata mr_emptyn mrdataenn mrlastcycn cmd brst
lucent technologies inc. 49 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core master controller detailed description (continued) 5-7369(f) figure 14. master read burst (pci bus, 32-bit) ta b le 15. dual-port master read, speci ed burst length 1. when maenn, mrdataenn, and ma_fulln are deasserted high, the master interface is idle. 2. when maenn is asserted low, a command/address phase is in progress. 3. maenn must be asserted low for command/address data to transfer and state to change. 4. maenn must be deasserted high and mrdataenn must be asserted low to execute the data phase. 5. next state = 0 if mrlastcycn is asserted low (end of master read data phase). 6. next state = 0 if mwlastcycn is asserted low (end of master command/address phase). mstatecntr next state of mstatecntr description data on bus datafmfpgax[3:0] datafmfpga[31:0] data on bus datatofpga[31:0] notes 00 idle, or data[15:0] x 4 xxxxxxxx 16 pcidata[31:0] 1, 4, 5 01 or 0 burst length, command word, or data[63:32] burst length, command word pcidata[63:32] 2, 3, 4, 5, 6 10 or 2 address[31:0] x 4 , pciaddress[31:0] ? 2, 3, 6 20 address[63:32] x 4 , pciaddress[63:32] ? 2, 3, 6 t0 t1 t2 t3 t4 t5 t6 t7 t8 adrs d0 d1 d2 d3 cmd be0 be1 be2 be3 clk framen ad c_ben irdyn devseln trdyn stopn
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 50 lucent technologies inc. lattice semiconductor pci bus core master controller detailed description (continued) ta b le 16. quad-port master read, duplicate burst length 1. when maenn, mrdataenn, and ma_fulln are deasserted high, the master interface is idle. 2. when maenn is asserted low, a command/address phase is in progress. 3. maenn must be asserted low for command/address data to transfer and state to change. 4. maenn must be deasserted high and mrdataenn must be asserted low to execute the read data phase. 5. next state = 0 if mrlastcycn is asserted low (end of master read data phase). 6. next state = 0 if mwlastcycn is asserted low (end of master command/address phase). ta b le 17. quad-port master read, speci ed burst length 1. when maenn, mrdataenn, and ma_fulln are deasserted high, the master interface is idle. 2. when maenn is asserted low, a command/address phase is in progress. 3. maenn must be asserted low for command/address data to transfer and state to change. 4. maenn must be deasserted high and mrdataenn must be asserted low to execute the read data phase. 5. next state = 0 if mrlastcycn is asserted low (end of master read data phase). 6. next state = 0 if mwlastcycn is asserted low (end of master command/address phase). mstatecntr next state of mstatecntr description data on bus mwdata[17:0] data on bus mrdata[15:0] notes 00 idle xx 2 xxxx 16 ?1 01 or 0 command word or data[15:0] command word pcidata[15:0] 2, 3, 4, 5, 6 12 or 0 address[15:0] or data[31:16] xx 2 , pciaddress[15:0] pcidata[15:0] 2, 3, 4, 5, 6 23 or 0 address[31:16] or data[47:32] xx 2 , pciaddress[15:0] pcidata[47:32] 2, 3, 4, 5, 6 34 or 0 address[47:32] or data[63:48] xx 2 , pciaddress[47:32] pcidata[63:48] 2, 3, 4, 5, 6 40 address[63:48] xx 2 , pciaddress[63:48] ? 2, 3, 6 mstatecntr next state of mstatecntr description data on bus mwdata[17:0] data on bus mrdata[15:0] notes 00 idle xx 2 xxxx 16 ?1 01 command word or data[15:0] command word pcidata[15:0] 2, 3, 4, 5, 6 12 or 0 burst length or data[31:16] burst length pcidata[31:16] 2, 3, 4, 5, 6 23 or 0 address[15:0] or data[47:32] xx 2 , pciaddress[15:0] pcidata[47:32] 2, 3, 4, 5, 6 34 or 0 address[31:16] or data[63:48] xx 2 , pciaddress[15:0] pcidata[63:48] 2, 3, 4, 5, 6 45 or 0 address[47:32] or data[63:48] xx 2 , pciad- dress[47:32] ? 2, 3, 6 50 address[63:48] xx 2 , pciad- dress[63:48] ? 2, 3, 6
lucent technologies inc. 51 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core target controller detailed description ta rg et fifo interface overview the target fifo interface consists of two transfer phases: command/address followed by data. this sequence must be followed with the assertion of twlastcycn indicating the completion of each phase. the pci address and command are always provided by the target fifo interface with the address trans- f erred on the data paths for the speci c mode. in any port mode, the command and address are transferred during the same cycle with the target command trans- f erred on a separate bus tcmd . the command/address phase is followed by data transfer. for target writes, write data with byte enables will be provided from the t arget, whereas for target reads, the target will receive its data from the fpga application. all types of data are transferred on the data paths de ned by the opera- tional mode (dual- or quad-port). ta rg et state counter the target fifo interface provides a state counter, tstatecntr[3:0] , that informs the fpga application of its current state (table 19). this state counter deter- mines what data is being provided to the fpga appli- cation by the target fifo interface during the command/address or write data phases, or what is e xpected from the fpga application during the read data phases. the state counter transitions from one state to another in a predetermined manner. table 20 through table 23 detail the sequencing of the tstate- cntr and the data transferred for target write and read transactions. the value on bus tstatecntr can be used to minimize fpga logic or verify proper operation. the data pro- vided by the target fifo interface to the fpga appli- cation is accompanied by a value on tstatecntr[3:0] . this value can be directly used by the fpga applica- tion to determine the proper orientation of the target command, address and/or write data. this eliminates the need for logic in the fpga to duplicate a state counter. the data required from the fpga application by the target during the read data phase is also de ned by the value on tstatecntr . however, the state counter value being sent to the fpga is in the same cycle that the data is sent from the fpga application. here, the value provided by the target fifo interface can be used to determine the next state, since current since current data, phase, enables, and state transi- tions are known. ta rg et address compare and bar size the target fifo interface provides the following two f eatures to reduce overhead when transferring the pci start target address during the command/address phase. first, the target fifo interface detects the page size of the base address register (bar) that decoded the current pci address, and only transfers the address b ytes necessary to cover the page size. second, the target fifo interface provides a holding register which is used to compare the address of the previous target transaction to the current one. if there is a match, the most signi cation address information is not transferred, providing the bar size is greater than the data bus size for quad- or dual-port mode. this will cover address bits [63:48] in quad-port and bits [63:32] in the dual-port mode. this option is enabled through the fpsc con guration manager of the fpsc design kit. ta rg et write operation delayed transactions, target memory write t arget memory write operations cannot be processed as delayed (delayed transactions: pci speci cation 2.2: section 3.3.3.3), and are always posted. the tar- get will only retry a memory write transaction if a cur- rent target transaction is in progress ( treqn is asserted) or t_retryn is asserted. once the target determines that it is the intended recipient, it asserts devseln and trdyn and begins storing data into the t arget write fifo, providing space is available. delayed transactions, target i/o write t arget i/o write operations can be posted ( deltrn = 1) or delayed ( deltrn = 0), and always disconnect burst accesses into single accesses. for a delayed i/o write, the target records the pci bus command, address, and rst data word (32 or 64 bits) along with its byte enables (4 or 8 bits) during the initial access. the pci b us command and address are put in the target address fifo, and the data word and byte enables are put in the target write fifo. on the pci bus, the request is terminated in a retry (with the master unaware that the data was snooped), and the fpga application is informed that a target request is pending via the assertion of treqn . the transaction status at this time is dwr (delayed write request?see pci speci - cation 2.2: section 3.3.3.3.6), and subsequent requests will be terminated in retry until the fpga application processes the target transaction.
52 52 lucent technologies inc. orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 lattice semiconductor pci bus core target controller detailed description (continued) when the fpga application reads the target write fifo and empties it, the transaction status changes to d wc (delayed write completion), and the next target i/o write that matches the stored command, address, data, and byte enables will be disconnected with data, completing the transaction and clearing the target address and target write fifos. targ et con guration writes accesses of con guration space occur without any involvement of the fpga application. all con guration space accesses are disconnected with data on the rst data word and are thus restricted from bursting. ta rg et write wait-states all target write data is accepted with zero wait-states. when a target memory write operation lls the target write fifo, future response depends on signal twburstpendn . if it is deasserted, the target will gener- ate a disconnect without data on the next data cycle. if it is asserted, the target will insert up to eight wait- states and then disconnect without data if the fifo remains full. target i/o operations cannot ll the fifo because they do not burst, disconnecting with data on the rst dword. command/address setup when the target has accepted a pci target transac- tion, it will inform the fpga application by asserting the signal treqn . the fpga application can then transfer the pci start address, target command word, and data in the speci c order prescribed in table 20 through ta b le 23, for the operational mode (quad- and dual- port). the address data is transferred via bus twdata (quad-port mode) or datatofpga (dual-port mode with f o_sel = 1) when taenn is asserted. taenn should only be asserted when treqn is active and t_ready is active. the command/address phase ends with the assertion of twlastcycn . the target command word (pci bus command) and decoded bar register are transferred on the separate buses, tcmd and bar respectively, and are valid when treqn is active. the number of cycles necessary to send the target address can vary. the target fifo interface will ana- lyze the size of the decoded bar and perform the min- imal number of cycles to completely transfer the page of the address. for example, if the bar is 256k in size, only the lower 18 bits of address is required by the fpga application. this will result in one clock address transfer for dual-port (32-bits) and two for the quad-port (16-bits). accompanying the address data during the assertion of taenn , is information on the current target transaction (table 18). dual-address or 64-bit address is indicated during the address phase by twdata[16] (quad-port) or datatofpgax[0] (dual-port with f o_sel = 1) being asserted. if the current transaction is a burst, twdata[17] (quad-port) or datatofpgax[1] (dual-port with f o_sel = 1) will be asserted. all burst transactions (burst indication bit active) and 64-bit agents ( pci_64bit = 1) will have the target data aligned on a 64-bit address boundary ( ad2 = 0), even if the pci start address starts on a 32-bit address with ad2 = 1. if the burst transaction on the pci bus starts on a odd 32-bit address boundary ( ad2 = 1), the data phase start address will be on a 64-bit address bound- ary ( ad2 = 0). likewise, the data phase will also end on a 64-bit address boundary, therefore the number of transfers between the target fifo interface and the fpga application will always be even for burst transac- tions and 64-bit agents ( pci_64bit = 1). ta b le 18. bit destinations for target command/address phase * refer to pci speci cation 2.2 section 3.1. bits name description quad-port dual-port ta rg et address word (pci core fpga) 17 bi burst indication twdata[17] datatofpgax[1] 16 da dual-address indication twdata[16] datatofpgax[0] 15:0 adrs address twdata[15:0] datatofpga[31:0] ta rg et command word (pci core fpga) 3:0 cmd pci command code* tcmd[3:0] tcmd[3:0]
lucent technologies inc. 53 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core target controller detailed description (continued) f or a write burst transaction to an odd address ( ad2 = 1), the rst write data word transferred to the fpga applica- tion will have all its byte enables deasserted and can be discarded. for target read transactions to an odd address ( ad2 = 1), the rst read data word provided by the fpga application is discarded by the target fifo interface. f or single transaction (burst indication bit deasserted) on 32-bit pci bus ( pci_64bit = 0), the target fifo interface handles all data alignment. the received address is valid as transferred, with the data phase aligning to this address. no extra data is transferred or discarded. ta b le 19. target state counter (tstatecntr) values and the corresponding bus data tstatecntr[3:0] dual-port mode (32-bit ports) quad-port mode (16-bit ports) data on bus datatofpga data on bus datafmfpga data on bus twdata data on bus trdata 0 adrs[31:0] data[31:0] adrs[15:0] data[15:0] 1 adrs[63:32] data[63:32] adrs[31:16] data[31:16] 2? ? adrs[47:32] data[47:32] 3? ? adrs[63:48] data[63:48] 4 data[31:0] ? data[15:0] ? 5 data[63:32] ? data[31:16] ? 6? ? data[47:32] ? 7? ? data[63:48] ? 8 ??? ? 9 ??? ? a ??? ? b ??? ? c ??? ? d ??? ? e ??? ? f ??? ?
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 54 lucent technologies inc. lattice semiconductor pci bus core target controller detailed description (continued) write data transfer the fpga application enters the write data phase by deasserting taenn and asserting twdataenn . on every cycle that twdataenn is asserted, the fpga applica- tion receives write data and its associated byte enables from the target write data fifo (64 32-bit words; 32 64-bit words) via bus twdata (quad-port mode) or datatofpga (dual-port mode with f o_sel = 1), provid- ing the write data fifos are not empty ( tw_emptyn = 1). twdataenn must not be asserted when the write data fifos are empty ( tw_emptyn is asserted). note that tw_emptyn can be updated on the same clock edge as twdataenn is sampled. the distinction between a burst write and a single access is provided by the burst indication bit ( twdata[17] (quad-port); datatofpgax[1] (dual-port with f o_sel = 1), or behavior of the twlastcycn signal during the data phase. when twlastcycn is asserted, this signal informs the fpga application of the end of the write data phase. twlastcycn will remain deas- serted with every write data element except the last element on bus twdata (quad-port mode) or datatof- pga (dual-port mode with f o_sel = 1). for example, on a single 32-bit word transfer in dual-port mode, twlastcycn would be asserted during the entire write data phase, since the last data phase is the only data phase of this transfer. when executing on a 64-bit pci bus ( pci_64bit = 1) or a burst target write, the write data transferred from the fpga application is aligned on 64-bit address bound- aries. this alignment may transfer extra padding data from the fifos for activity during 32-bit pci transfers. f or transfers starting at an odd 32-bit pci address ( ad2 = 1), the fpga application will receive a 32-bit padding data word at the beginning of the write data phase. for burst transfers starting at an even pci address ( ad2 = 0) with an odd number of 32-bit data w ords, a 32-bit padding data word will be received at the end of the data phase. padding data words are indi- cated by data words with all of its byte enables deas- serted. f or single 32-bit transactions (burst indication bit deas- serted) on 32-bit pci buses ( pci_64bit = 0), the target fifo interface will perform proper data alignment. dur- ing the data phase, the fpga application will only receive the 32-bit data word, and no padding words are present. ta rg et write data fifo empty/almost empty when the target write fifo contains four or fewer 64-bit data elements, the target fifo interface asserts tw_aemptyn the fifo almost empty indicator. this allows some latency to exist in the fpga?s response without risking overreading the fifo. when the fpga application has read all data out of the target write fifo, the target fifo interface asserts tw_emptyn , the fifo empty indicator. since data can be simulta- neously written to, and read from, the target write fifo, both tw_aemptyn and tw_emptyn can change states in either direction multiple times in the course of a burst data transfer. ta rg et write termination t arget write termination will be by normal master termi- nation, disconnect associated with a full target write data fifo, retry associated with a pending target transaction, or a reset by r stn . on the target fifo interface, twlastcycn signals when the last item remaining in the target write fifo has been received by the fpga application (although the actual pci bus transaction may have completed much earlier). the target fifo interface then signals end of transaction to the fpga application by deasserting treqn f or at least one clock. if treqn subsequently reas- serts, this indicates a new, unrelated transaction. reset the fpga application can apply a reset signal to place the target fifo interface logic in a known state, clear- ing the target fifos and resetting tstatecntr . the reset signal, t foclrn , is asynchronous and therefore should be asserted for a minimum of one clock cycle and deasserted for a minimum of one clock cycle before continuing. it is not recommended to assert t foclrn while a cur- rent pci transaction is in progress ( treqn is asserted), since proper pci bus termination is not guaranteed. only r stn will reset the internal target pci state machines, while a pci transaction is in progress.
lucent technologies inc. 55 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core target controller detailed description (continued) example: target write to con guration space transaction figure 15 shows the timing on the pci interface for a target write to con guration space. con guration space accesses occur without any involvement of the fpga interface. all con guration space accesses are disconnected with data on the rst data word and are thus restricted from bursting. address decode speed is medium, and the t arget signals that it is ready to receive the word of data by asserting trdyn one cycle after devseln is asserted. 5-7370(f) figure 15. target con guration write (pci bus, 32-bit) t0 t1 t2 t3 t4 t5 t6 address data cfg wr byte enables clk framen ad c_ben idsel irdyn devseln trdyn stopn
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 56 lucent technologies inc. lattice semiconductor pci bus core target controller detailed description (continued) example: target write i/o figure 16 shows the timing on the pci bus for a target i/o write which is posted; that is, the operation completes on the pci bus immediately. the target terminates the i/o write request by disconnecting with data on the rst word, thus disallowing bursting. f or a delayed target i/o write, the initial access would terminate with a retry although the target transaction has been snooped and forwarded on to the fpga application. retry terminations will continue on all future accesses until the fpga application has nished processing the target i/o write transaction. on the next access of this tar- get i/o write, the target terminates the i/o write request by disconnecting with data on the rst word, also disallow- ing bursting. the fpga interface timing is as shown in figure 18 and figure 19 for dual- and quad-port respectively. the fpga interface timing is similar for target i/o writes and target single memory writes, and is described below in the single target write fifo interface section. 5-7371(f) figure 16. target i/o write, nondelayed (pci bus, 32-bit) t0 t1 t2 t3 t4 t5 t6 address data io wr byte enables clk framen ad c_ben irdyn devseln trdyn stopn
lucent technologies inc. 57 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core target controller detailed description (continued) ta rg et write memory, single-word transaction figure 17 shows the timing on the pci bus, for a target memory write of a single word. the timing on the pci inter- f ace (figure 17) is similar to that of a posted i/o write (figure 16) except that, since bursts to memory space are allowed, the signal stopn is not asserted. 5-7373(f) figure 17. target memory single write (pci bus, 32-bit) single target write fifo interface the fifo interface timing is as shown in figure 18 and figure 19 for dual- and quad-port respectively. the inter- f ace timing is similar for all target i/o writes and target single memory writes, since the target fifo interface is uni- fo rm across all target accesses. the timing on the interface (figure 18 for dual-port) shows the rst indication to the fpga application that a new operation is pending by the assertion of target request ( treqn ). when treqn is valid, the fpga application begins the command/address phase by asserting target address enable ( taenn ) and accepting the command from bus tcmd and address from bus datatofpga ( x ) (with f o_sel = 1). if applicable, the dual-address indication bit accom- panies the address on datatofpga[0] , whereas for the single access on a 32-bit pci bus ( pci_64bit = 0) the burst indication bit ( datatofpga[1] ) will be desasserted. the fpga application continues to receive new address data ( taenn asserted) on every clock until twlastcycn is asserted, indicating the end of the command/address phase. see command/address section for notes regarding address transfer and alignment. the write data phase will follow, by deassertion of taenn , and assertion of target write data enable ( twdataenn ). twdataenn can only be asserted while tw_emptyn is deasserted, indicating that write data is available in the write data fifos. while twdataenn is asserted, the fpga application will receive target write data on bus datatofpga (with f o_sel = 1). the fpga application is informed that the last component of the data phase is being presented when twlastcycn is asserted. since this is a single access on a 32-bit data bus (assuming datatofpgax[1] = 0 dur- ing command/address phase, pci_64bit = 0), the rst and only data phase is the last data of the write data phase. t0 t1 t2 t3 t4 t5 address data mem wr byte enables clk framen ad c_ben irdyn devseln trdyn stopn
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 58 lucent technologies inc. lattice semiconductor pci bus core target controller detailed description (continued) f or quad-port mode (figure 19), the address and write data are transferred on the bus twdata in 16-bit segments. the address will be split into two 16-bit components with the lsb being transferred rst. if applicable, the dual- address indication accompanies the address on twdata[16] , whereas for a single access on a 32-bit pci bus ( pci_64bit = 0) the burst indication bit ( twdata[17] ) will be deasserted. assuming a bar size greater than 16 bits, the address phase will require two clock cycles, and twlastcycn will be asserted on the nal or msb component of the address. the data phase will also require two clock cycles to transfer a single 32-bit write data word across the 16-bit bus. twdataenn can only be asserted while tw_emptyn is deasserted, indicating that write data is available in the write data fifos. while twdataenn is asserted, the fpga application will receive target write data on bus twdata . twlastcycn will be deasserted for all 16-bit components of the write data phase, except for the nal 16-bit compo- nent, where it is asserted. 5-7354(f) figure 18. target write single (fifo interface, dual-port) 1t0t1t 2t3 0 4 0 cmd adrs data fclk t_ready tstatecntr treqn tcmd datatofpga fifo_sel taenn tw_emptyn twdataenn twlastcycn
lucent technologies inc. 59 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core target controller detailed description (continued) 5-7362(f) figure 19. target write single (fifo interface, quad-port) example: target write memory burst transaction figure 20 shows the timing on the pci bus for a target memory write burst of four 32-bit words. the timing on the pci interface is typical for a medium-speed decode target. note that trdyn is asserted at the earliest possible time, which is concurrent with assertion of devseln . in the example of a 4-word burst, the target write fifo is not lled, so execution continues to completion. this would also be the case for a burst of any length when the fpga appli- cation is capable of unloading the fifo as fast as the pci interface is loading it. if the target write fifo becomes full, the target can disconnect without data on the rst data word it cannot accept ( twburstpendn = 1), or insert up to eight wait-states ( twburstpendn = 0). the timing on the dual-port fifo interface (figure 21) shows the rst indication to the fpga application that a new operation has begun by the assertion of target request ( treqn ). when treqn is valid, the fpga application begins the command/address phase by asserting target address enable ( taenn ) and accepting the command from bus tcmd and address from bus datatofpga ( x ) (with f o_sel = 1). a burst operation and dual-address indication accompanies the address on datatofpgax[1] and datatofpgax[0] respectively. the fpga application continues to receives new address data ( taenn asserted) on every clock until twlastcycn is asserted, indicating the end of the command/address phase. see command/address section for notes regarding address transfer and alignment. 1t0t1t 2t3t4t5 0 1 4 5 0 cmd adrs0 adrs1 d0 d1 fclk tstatecntr t_ready treqn tcmd twdata taenn tw_emptyn twdataenn twlastcycn
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 60 lucent technologies inc. lattice semiconductor pci bus core target controller detailed description (continued) the write data phase will follow, by deassertion of taenn , and assertion of target write data enable ( twdataenn ). twdataenn can only be asserted while tw_emptyn is deasserted, indicating that write data is available in the write data fifos. while twdataenn is asserted, the fpga application will receive target write data on bus datatofpga (with f o_sel = 1), and write byte enables on datatofpgax . the fpga application is informed that the last compo- nent of the data phase is being presented when twlastcycn is asserted. since this is a burst access ( datatofp- gax[1] = 1 during command/address phase), the twlastcycn is deasserted for the entire data phase expect the last data of the write data phase. after receiving twlastcycn at the end of the data phase, twdataenn must be deasserted by the fpga application. see write data transfer section for notes regarding data alignment on bursts. f or quad-port mode (figure 22), the address and write data is transferred on the bus twdata in 16-bit segments. if necessary, the address will be split into two 16-bit components with the lsb being transferred rst. a burst opera- tion and dual-address indication accompanies the address on twdata[17] and twdata[16] respectively. assuming the bar size is greater than 16 bits, the address phase will require two clock cycles, and twlastcycn will be asserted on the nal or msb component of the address. the data phase will also require two clock cycles to trans- f er every 32-bit write data word across the 16-bit bus. twlastcycn will be deasserted for all 16-bit components of the write data phase, except for the nal 16-bit component where it is asserted. see write data transfer section for notes regarding write data alignment. 5-7374(f) figure 20. target memory write burst (pci bus, 32-bit) t0 t1 t2 t3 t4 t5 t6 t7 t8 address d0 d1 d2 d3 mem wr be0 be1 be2 be3 clk framen ad c_ben irdyn devseln trdyn stopn
lucent technologies inc. 61 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core target controller detailed description (continued) 5-7355(f) figure 21. target write burst (fifo interface, dual-port) 1t0t 1t2t3t4t5t6t7 0 4 5 4 5 0 cmd adrs d0 d1 d2 d3 fclk t_ready tstatecntr treqn tcmd datatofpga fifo_sel taenn tw_emtpyn twdataenn twlastcycn
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 62 lucent technologies inc. lattice semiconductor pci bus core target controller detailed description (continued) 5-7363(f) figure 22. target write burst (fifo interface, quad-port) ta b le 20. dual-port target write 1. when treqn is deasserted high, the target interface is idle. 2. when taenn is asserted low, a command/address phase is in progress. 3. taenn must be asserted low for command/address data to transfer and state to change. 4. taenn must be deasserted high and twdataenn must be asserted low to execute the data phase. 5. next state = 0 if twlastcycn is asserted low (end of target write data). 6. next state = 4 if twlastcycn is asserted low (end of target command/address phase). tstatecntr next state or tstatecntr description data on bus datafmfpgax[3:0], datafmfpga[31:0] notes 00 idle x 4 , xxxxxxxx 16 1 01 or 4 address[31:0] x 2 , burst, dual-address, pciaddress[31:0] 2, 3, 6 14 address[63:32] x 2 , burst, dual-address, pciaddress[63:32] 2, 3, 6 45 or 0 data[31:0] ben[3:0], pcidata[31:0] 4, 5 54 or 0 data[63:32] ben[7:4], pcidata[63:32] 4, 5 1t0t 1t2t3t4t5t6t7t8t9t10 0 1 4 5 6 7 4 5 6 7 0 cmd adrs0 adrs1 d0 d1 d2 d3 d4 d5 d6 d7 fclk t_ready tstatecntr treqn tcmd twdata taenn tw_emptyn twdataenn twlastcycn
lucent technologies inc. 63 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core target controller detailed description (continued) ta b le 21. quad-port target write 1. when treqn is deasserted high, the target interface is idle. 2. when taenn is asserted low, a command/address phase is in progress. 3. taenn must be asserted low for command/address data to transfer and state to change. 4. taenn must be deasserted high and twdataenn must be asserted low to execute the data phase. 5. next state = 0 if twlastcycn is asserted low (end of target write data). 6. next state = 4 if twlastcycn is asserted low (end of target command/address phase). ta rg et read operation a target read operation presents unique demands on the fpga application because only in this operation does the target request data that is needed to complete the transaction after the pci transaction has already begun on the pci bus. target latency rules require that the data be acquired quickly or that the target terminate the transac- tion with a retry/disconnect. also, once the transfer process is underway, the target usually does not know how m uch more data will be requested. the target must prefetch data so that it will be available if needed. delayed transactions a signal ( deltrn ) from the fpga application in uences the behavior of target read and i/o write operations. when deltrn is asserted-low, the target controller logic will enter delayed mode on incoming target reads (memory or i/o) and i/o writes. delayed mode will issue a retry to the external master, but store internally the pci address, command, and write data (if an i/o write). the retry frees up the pci bus for other activity, while the fpga applica- tion processes the target request. when the external master attempts the same transaction again to the target, read data will be transferred if the target read fifos are nonempty. when this signal is inactive-high, the target controller will generate wait-states, until either the fifo becomes not empty and transmits the read data, or until the maximum initial latency value (16 or 32 clock cycles in the fpsc con guration manager) has been reached. if deltrn is deasserted, twburstpendn m ust be asserted. this signal should be inactive when minimum initial latency is desired on the initial data word, at the expense of ov erall pci bus ef ciency. signal deltrn affects the transaction?s behavior on the initial data word, whereas signal trburstpendn affects subsequent data latency when the target read data fifo empties. when trburstpendn is inactive, a disconnect without data results from an attempt to read from an empty read data fifo, after data has been transferring on the pci bus. with trburstpendn active, the target will wait for data from the fifo by inserting w ait-states (up to the maximum subsequent latency value of eight, at which time a disconnect without data will be generated). asserting trburstpendn will minimize latency for this transaction?s data at the expense of overall pci b us ef ciency. trburstpendn must remain static throughout a target read transaction. tstatecntr next state or tstatecntr description data on bus twdata[17:0] notes 00 idle xx 2 , xxxx 16 1 01 or 4 address[15:0] burst, dual-address, pciaddress[15:0] 2, 3, 6 12 or 4 address[31:16] burst, dual-address, pciaddress[31:16] 2, 3, 6 23 or 4 address[47:32] burst, dual-address, pciaddress[47:32] 2, 3, 6 34 address[63:48] burst, dual-address, pciaddress[63:48] 2, 3, 6 45 data[15:0] ben[1:0], pcidata[15:0] 4 56 or 0 data[31:16] ben[3:2], pcidata[31:16] 4, 5 67 data[47:32] ben[5:4], pcidata[47:32] 4 74 or 0 data[63:48] ben[7:6], pcidata[63:48] 4, 5
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 64 lucent technologies inc. lattice semiconductor pci bus core target controller detailed description (continued) although, the signal deltrn is used to enter into delayed mode, all target read transactions automati- cally enter delayed mode on a retry. for example, if the t arget inserted 16/32 wait-states on the initial read access and no data was provided to the target read data fifo causing a disconnect, the transaction will revert into delayed mode. on the following external master accesses, if no data was available in the target read data fifo, an immediate retry would be issued with no wait-states. i/o reads i/o reads differ only from memory reads in that i/o reads always perform a disconnect with data on the rst data element read from the target read fifo. command/address setup when the target has accepted a pci target transac- tion, it will inform the fpga application by asserting the signal treqn . the fpga can then transfer the pci start address, target command word, and data in the spe- ci c order prescribed in table 22 through table 23, for the operational mode (quad- and dual-port). the address data is transferred via bus twdata (quad-port mode) or datatofpga (dual-port mode with f o_sel = 1) when taenn is asserted. taenn should only be asserted when treqn is active and t_ready is active. the command/address phase ends with the assertion of twlastcycn . the target command word (pci bus command) and decoded bar register are transferred on the separate buses tcmd and bar , respectively, and are valid when treqn is active. the number of cycles necessary to send the target address can vary. the target fifo interface will ana- lyze the size of the decoded bar, and performed the minimal number of cycles to completely transfer the page of the address. for example, if the bar is 256k in size, only the lower 18 bits of address is required by the fpga application. this will result in one clock address transfer for dual-port (32-bits) and two for the quad-port (16-bits). accompanying the address data during the assertion of taen , is information on the current target transaction. dual-address or 64-bit address is indicated during the address phase by twdata[16] (quad-port) or datatofp- gax [ 0 ] (dual-port with f o_sel = 1) being asserted. if the current transaction is a burst, twdata[17] (quad- port) or datatofpgax[1] (dual-port with f o_sel = 1) will be asserted. all burst transactions (burst indication bit active) and 64-bit agents ( pci_64bit = 1) will have the target data aligned on a 64-bit address boundary ( ad2 = 0), even if the pci start address starts on a 32-bit address with ad2 = 1. if the burst transaction on the pci bus starts on a odd 32-bit address boundary ( ad2 = 1), the data phase start address will be on a 64-bit address bound- ary ( ad2 = 0). likewise, the data phase will also end on a 64-bit address boundary, therefore the number of transfers between the target fifo interface and the fpga application will always be even. for target read transactions starting at an odd 32-bit address bound- ary, the rst read data word is ignored by the target controller, but needs to be transferred by the fpga application. f or single transactions (burst indication bit deasserted) on a 32-bit bus ( pci_64bit = 0), the target fifo inter- f ace will handle all data alignment. the received address is valid, with the data phase aligning to the address. no extra data is transferred or padded. read data transfer the fpga application enters the read data phase by deasserting taenn and asserting trdataenn . on every cycle that trdataenn is asserted, the fpga application provides read data to the target read fifo (64-, 32-bit w ords; 32-, 64-bit words) via bus trdata (quad-port mode) or datafmfpga (dual-port mode). trdataenn m ust not be asserted when the read data fifos are full ( tr_fulln is asserted). all byte lanes are passed on to the pci bus, therefore no byte enables are required. note that tr_fulln can be updated on the same clock edge as trdataenn is sampled. the distinction between a burst read and a single access on a 32-bit bus ( pci_64bit = 0) is provided by the burst indication bit, twdata[17] (quad-port) or datatofpgax[1] (dual-port with f o_sel = 1), along with the behavior of the trlastcycn signal during the data phase. when trlastcycn is asserted, this signal informs the fpga application of the end of the read data phase, and that the master has disconnected. trlastcycn will remain deasserted with every read data element except the last element on bus trdata (quad- port mode) or datafmfpga (dual-port mode). trlast- c ycn can remain asserted throughout a single (non- b urst) target read data phase. on a 32-bit pci bus ( pci_64bit = 0). for example, on a single 32-bit word transfer in dual-port mode, trlastcycn would be asserted during the entire read data phase, since the last data phase is the only data phase of this transfer. after receiving an asserted trlastcycn , the fpga application should deassert trdataenn . f or trlastcycn to be asserted, trdataenn must be asserted.
lucent technologies inc. 65 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core target controller detailed description (continued) when executing a burst target read, or on a 64-bit bus ( pci_64-bit = 1), the read data transferred from the fpga application must be aligned on 64-bit address boundaries, which may require transferring extra pad- ding data to proper ll the fifos for activity on 32-bit pci buses. for transfers starting at an odd 32-bit pci address ( ad2 = 1), the fpga application will transfer a e xtra 32-bit padding data word at the beginning of the read data phase. for burst transfers starting at an even pci address ( ad2 = 0) with an odd number of 32-bit data words, a extra 32-bit padding data word will be transferred at the end of the data phase. padding data w ord can be any data words. f or single 32-bit transactions (burst indication bit deas- serted) on a 32-bit pci bus ( pci_64bit = 0), the target fifo interface handles all data alignment. the received address is valid with the data phase aligning to the address. no extra padding of data is necessary. at some times, the fpga application may not have v alid data to transfer to the target read fifo or the read data fifos may be lled, therefore trdataenn will be deasserted. if the external master disconnects dur- ing this time, trlastcycn will not be produced. in this situation, the fpga application must monitor the signal t_ready f or an indication that the external master is ter- minating the target transaction. when t_ready is deas- serted, the fpga application will need to assert trdataenn to receive trlastcycn and properly reset the t arget fifo interface. during the time that t_ready is deasserted, the target is clearing the target read fifos and no data will be transferring to the pci bus. any read data transferred will be ignored during this time. burst transfers are performed as continuous data phases if read data is available in the target read data fifo. at completion of target read bursts, there may result a discarding of unused data elements supplied in e xcess of the external master transaction?s needs. all data within the target read fifos is cleared after mas- ter termination. ta rg et read fifo hold the signal trpcihold can be asserted to delay the start of transfer of data during a target read operation, i.e., trdyn asserted. while trpcihold is active, read data can be transferred from the fpga application into the t arget read fifos. when the target read fifos become full or trpcihold is deasserted, the target read operation will begin on the pci bus. use of this signal can result in more ef cient utilization of pci bus band- width by causing up to a full buffer contents to be b ursted, without wait-states, whenever the external master accesses the target. fifo full/almost full when the target read fifo contains four or fewer 64- bit empty locations, the target fifo interface asserts tr_afulln , the almost full indicator. this allows some latency to exist in the fpga?s response without risking over lling the fifo. when all locations in the target read fifo are full, the target asserts tr_fulln , the full indicator. since the data can be simultaneously written to and read from the target read data fifo, both tr_afulln and tr_fulln can change states in either direction multiple times in the course of a burst data transfer. t ermination t arget read termination will be by normal master termi- nation, disconnect associated with a empty target read data fifo, retry associated with a pending target transaction, or a reset by r stn . on the target fifo interface, trlastcycn signals when the external master has gathered all of the necessary data from the target read fifo, even if extra data remains in the target read fifo. the target fifo inter- f ace signals end of transaction to the fpga application by deasserting treqn for at least one clock. if treqn subsequently reasserts, this indicates a new, unrelated transaction. reset the fpga application can apply a reset signal to place the target fifo interface logic in a known state, clear- ing the target fifos and resetting tstatecntr . the reset signal, t foclrn , is asynchronous and therefore should be asserted for a minimum of one clock cycle and deasserted for a minimum of one clock cycle before continuing. it is not recommended to assert t foclrn while a cur- rent pci transaction is in progress ( treqn is asserted), since proper pci bus termination is not guaranteed. only r stn will reset the internal target pci state machines, while a pci transaction is in progress.
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 66 lucent technologies inc. lattice semiconductor pci bus core target controller detailed description (continued) example: target read from con guration space figure 23 shows the timing on the pci interface for a target read from con guration space. accesses of con gura- tion space occurs without any involvement of the fpga interface. all con guration space accesses are discon- nected with data on the rst data word, and are thus restricted from bursting. address decode speed is medium, and the pci bus core signals that it is supplying the word of data by asserting trdyn one cycle after devseln is asserted. 5-7375(f) figure 23. target con guration read (pci bus, 32-bit) t0 t1 t2 t3 t4 t5 t6 address data cfg rd byte enables clk framen ad c_ben idsel irdyn devseln trdyn stopn
lucent technologies inc. 67 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core target controller detailed description (continued) example: target single read i/o, delayed transaction figure 24 shows the timing on the pci for a target i/o read that is handled as a delayed transaction ( deltrn = 0). three transactions are shown. the rst is the initial read in which the target latches the command, address, and b yte enables. the target then issues a retry, obligating the remote master to continue to issue that identical request until data is transferred. meanwhile, the latched information will be transferred to the fpga application via the tar- get fifo interface. in the second transaction, as shown in figure 24, all subsequent read or write requests to memory or i/o space will result in retries, until the read data fifo becomes nonempty. the third transaction is the nal transaction that completes the transfer of read data. the timing on this third transaction is identical to the tim- ing of the rst except that trdyn accompanies stopn to indicate the disconnect with data. the fpga interface timing is shown in figure 27 and figure 28 for dual- and quad-port respectively. the fpga interface timing is similar for all target reads and is described below in the single target read fifo interface sec- tion. 5-7547(f) figure 24. target i/o read, delayed (pci bus, 32-bit) ta0 ta1 ta2 ta3 ta4 ta5 ta6 tb0 tb1 tb2 tb3 tb4 tb5 tb6 tc0 tc1 tc2 tc3 tc4 tc5 tc6 adrs adrs adrs data cmd bes cmd byte enables cmd byte enables clk framen ad c_ben irdyn devseln trdyn stopn transaction #1: address, byte enables, and command latched as a delayed read request. transaction #2: disconnected without data because read operation not completed. transaction #3: disconnected with data because read operation completed.
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 68 lucent technologies inc. lattice semiconductor pci bus core target controller detailed description (continued) example: target read i/o, nondelayed transaction figure 25, shows the timing on the pci bus for a target i/o read that is handled as nondelayed transaction ( deltrn = 1, trburstpendn = 0); that is, the operation waits on the pci bus while the fpga application is noti ed via the target fifo interface. the target accepts the transaction without issuing an immediate retry, but inserts wait- states (up to 16 or 32) until the requested data in placed in the target read fifo. if the fpga application cannot f etch the data within the initial/subsequent latency time, the target issues a retry. the target terminates the i/o read request by disconnecting with data on the rst word transformed, thus disallowing bursting. the fpga interface timing is as shown in figure 27 and figure 28 for dual- and quad-port respectively. the fpga interface timing is similar for all target reads and is described below in the single target read fifo interface sec- tion. 5-7546(f) figure 25. target i/o read, nondelayed (pci bus, 32-bit) t0 t1 t2 t3 tn0 tn1 tn2 tn3 x address x x data x x cmd: i/o rd byte enables byte enables x clk frame# ad[31:0] c/be[3:0]# irdyn# devsel# trdy# stop#
lucent technologies inc. 69 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core target controller detailed description (continued) example: target read memory, single-word, delayed transaction figure 26 shows the timing on the pci bus interface for a target single 32-bit memory read handled as a delayed transaction ( deltrn = 0). the timing on the pci interface (figure 26) is similar to that of a delayed i/o read (figure 24) except that stopn is not asserted here to cause disconnect with data. 5-7549(f) figure 26. target single memory read, delayed (pci bus, 32-bit) the fpga interface timing is as shown in figure 27 and figure 28 for dual- and quad-port respectively. the fpga interface timing is similar for all target reads and is described below in the single target read fifo interface sec- tion. transaction #1: address, byte enables, and command latched as a delayed read request. transaction #2: disconnected without data because read operation not completed. transaction #3: disconnected with data because read operation completed. ta0 ta1 ta2 ta3 ta4 ta5 ta6 tb0 tb1 tb2 tb3 tb4 tb5 tb6 tc0 tc1 tc2 tc3 tc4 tc5 tc6 adrs adrs adrs data cmd bes cmd byte enables cmd byte enables clk framen ad c_ben irdyn devseln trdyn stopn
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 70 lucent technologies inc. lattice semiconductor pci bus core target controller detailed description (continued) 5-7356(f) figure 27. target read single (fifo interface, dual-port) t0 t1 t2 t3 t4 0 cmd adrs data fclk t_ready tstatecntr treqn tcmd datatofpga fifo_sel taenn twlastcycn datafmfpga tr_fulln trdataenn trlastcycn
lucent technologies inc. 71 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core target controller detailed description (continued) 5-7364(f) figure 28. target read single (fifo interface, quad-port) t0 t1 t2 t3 t4 t5 t6 0 1 0 1 0 cmd adrs0 adrs1 d0 d1 fclk t_ready tstatecntr treqn tcmd twdata taenn twlastcycn trdata tr_fulln trdatenn trlastcycn
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 72 lucent technologies inc. lattice semiconductor pci bus core target controller detailed description (continued) example: target read memory, single-word, nondelayed transaction figure 29 shows the timing on the pci bus for a target single memory read that is handled as nondelayed ( deltrn = 1, trburstpendn = 0); that is, the operation waits on the pci bus while the fpga application is noti ed via the target fifo interface. the target accepts the transaction without issuing an immediate retry, but inserts wait- states (up to 16 or 32) until data is in placed in the target read fifo. if the fpga application cannot provide data within the initial latency time, the target issues a retry. the target terminates the single read request normally with data on the rst word transformed. 5-7548(f). figure 29. target memory read single, nondelayed transaction (pci bus, 32-bit) single target read fifo interface the fifo interface timing is as shown in figure 27 and figure 28 for dual- and quad-port respectively. the target fifo interface timing to the fpga application is similar for all target reads: delayed target i/o read, nondelayed t arget i/o read, delayed target memory read, and nondelayed target memory read. the timing on the fifo inter- f ace (figure 27 for dual-port) shows the rst indication to the fpga application that a new operation has begun by the assertion of target request ( treqn ). the fpga application begins the command/address phase by asserting t arget address enable ( taenn ) and accepting the command from the tcmd bus and address from bus datatofpga (with f o_sel = 1). a burst operation and dual-address indication accompanies the address on datatofpgax[1] and datatofpgax[0] respectively. the fpga application continues to receive address data until twlastcycn is asserted indicating the end of the command/address phase. see command/address section for notes regarding address transfer and alignment. the read data phase will follow, by deassertion of taenn , and assertion of target read data enable ( trdataenn ). trdataenn can only be asserted while tr_fulln is deasserted, indicating that space is available in the read data fifos. while trdataenn is asserted, the fpga application will transfer target read data on bus datafmfpga to the read data fifos. the fpga application is informed when the last component of the data phase was received when trlastcycn is asserted. in a single access on a 32-bit pci bus ( pci_64bit = 0), this is on the rst data phase. assuming this is a single access, ( datatofpgax[1] = 0 during command/address phase), the rst and only data phase is the last data of the read data phase. after receiving trlastcycn at the end of the data phase, trdataenn m ust be deasserted by the fpga application. trlastcycn can only be asserted when trdataenn is asserted. see read data transfer section for details on trlastcycn . t0 t1 t2 t3 tn0 tn1 tn2 tn3 address data mem rd byte enables byte enables clk framen ad c_ben irdyn devseln trdyn stopn devseln
lucent technologies inc. 73 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core target controller detailed description (continued) f or quad-port mode (figure 28), the address is transferred on the bus twdata in 16-bit segments. if necessary, the address will be split into two 16-bits components with the lsb being transferred rst. a burst operation and dual- address indication accompanies the address on twdata[17] and twdata[16] respectively. assuming a bar size g reater than 16 bits, the address phase will require two clock cycles, and twlastcycn will be asserted on the nal or msb component of the address. the data phase will also require two clock cycles to transfer every 32-bit read data word across the 16-bit bus from the fpga application. trlastcycn will be deasserted for all 16-bit components of the write data phase, except for the nal 16-bit component where it is asserted. trlastcycn can only be asserted when trdataenn is asserted. see read data transfer section for details on trlastcycn . example: target read memory burst, delayed transaction figure 30 shows the timing on the pci bus for a target memory burst read of four 32-bit words handled as a delayed transaction ( deltrn = 0). on the pci interface (figure 30), three transactions are shown. in the rst, the t arget responds to the request after determining that the address matches one of its bars by asserting devseln . however, since delayed transaction has been speci ed by the fpga application ( deltrn = 0), the target issues a retry since the target read fifo is empty. the target waits for the fpga application to load the target read fifo. until this occurs, all memory and i/o accesses result in retries as shown by the second transaction in figure 30. after the required read data is loaded, the actual data transfer will occur as shown in the third transaction in figure 30. the fpga interface timing is as shown in figure 31 and figure 32 for dual- and quad-port respectively. the target fifo interface timing to the fpga application is similar for all target burst reads and is described below for the tar- get read burst fifo interface. 5-7551(f) figure 30. target burst memory read, delayed (pci bus, 32-bit) transaction #1: address, byte enables, and command latched as a delayed read request. transaction #2: disconnected without data because read operation transaction #3: disconnected with data because read operation completed. ta0 ta1 ta2 ta3 ta4 ta5 ta6 tb0 tb1 tb2 tb3 tb4 tb5 tb6 tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 tc8 tc9 adrs adrs adrs d0 d1 d3 d4 cmd bes cmd byte enables cmd byte enables clk framen ad c_ben irdyn devseln trdyn stopn ad_del ad_del ad_del not completed.
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 74 lucent technologies inc. lattice semiconductor pci bus core target controller detailed description (continued) 5-7357(f) figure 31. target read burst (fifo interface, dual-port) t0 t1 t2 t3 t4 t5 t6 0 1 0 1 0 cmd adrs d0 d1 d2 d3 fclk t_ready tstatecntr treqn tcmd datatofpga fifo_sel taenn twlastcycn datafmfpga tr_fulln trdataenn trlastcycn
lucent technologies inc. 75 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core target controller detailed description (continued) 5-7365(f) figure 32. target read burst (fifo interface, quad-port) ta rg et read memory burst, nondelayed transaction figure 33 shows the timing on the pci bus interface, for a target memory burst read of four 32-bit words handled as a nondelayed transaction ( deltrn = 1, trburstpendn = 0). the operation starts and waits on the pci bus while the fpga application is noti ed via the target fifo interface. this is similar to that of an delayed target burst read (figure 30), except the target accepts the transaction without issuing an immediate retry, but inserts wait-states (up to 16 or 32) until data is in placed in the target read fifo. if the fpga application cannot provide data within the initial latency time, the target issues a retry. ta rg et read burst fifo interface the timing on the fpga interface (figure 31 for dual-port) shows the rst indication to the fpga application that a new operation has begun by the assertion of target request ( treqn ). the fpga application begins the command/ address phase by asserting target address enable ( taenn ) and accepting the command from the tcmd bus and address from bus datatofpga[0] (with f o_sel = 1). a burst operation and dual-address indication accompanies the address on datatofpgax[1] and datatofpgax[0] respectively. the fpga application continues to receives address data until twlastcycn is asserted indicating the end of the command/address phase. see command/ address setup section (see page 52) for notes on address transfer and alignment. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 0 1 0 1 2 3 0 1 2 3 0 cmd adrs0 adrs1 d0 d1 d2 d3 d4 d5 d6 d7 fclk t_ready tstatecntr treqn tcmd twdata taenn twlastcycn trdata tr_fulln trdataenn trlastcycn
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 76 lucent technologies inc. lattice semiconductor pci bus core target controller detailed description (continued) the read data phase will follow, by deassertion of taenn , assertion of target read data enable ( trdataenn ). trda- taenn can only be asserted while tr_fulln is deasserted, indicated that space is available in the read data fifos. while trdataenn is asserted, the fpga application will transfer target read data on bus datafmfpga to the read data fifos. the fpga application is informed when the last component of the data phase is need when trlast- c ycn is asserted. in a burst access, this is during the last data phase. assuming this is a burst access, ( datatofp- gax[1] = 1 during command/address phase), trlastcycn is deasserted during the read data phase except for the last data of the read data phase. after receiving trlastcycn at the end of the data phase, trdataenn must be deas- serted by the fpga application. trlastcycn can only be asserted when trdataenn is asserted. see read data tr ansfer section for details on trlastcycn . f or quad-port mode (figure 32), the address data is transferred on the bus twdata in 16-bit segments. the address will be split into two 16-bits components with the lsb being transferred rst. a burst operation and dual- address indication accompanies the address on twdata[17] and twdata[16] respectively. assuming a bar size g reater than 16 bits, the address phase will require two clock cycles for a 32-bit address, and twlastcycn will be asserted on the nal or msb component of the address. the data phase will also require two clock cycles to trans- f er every 32-bit read data word across the 16-bit bus trdata from the fpga application. trlastcycn will be deas- serted for all 16-bit components of the read data phase, except for the nal 16-bit component where it is asserted. 5-7550(f) figure 33. target memory burst read, nondelayed (pci bus, 32-bit) t0 t1 t2 t3 tn0 tn1 tn2 tn3 tn4 address d0 d1 d2 d3 mem rd be0 be0 be1 be2 be3 clk framen ad c_ben irdyn devseln trdyn stopn
lucent technologies inc. 77 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core target controller detailed description (continued) ta b le 22. dual-port target read 1. when treqn is deasserted high, the target interface is idle. 2. when taenn is asserted low, a command/address phase is in progress. 3. taenn must be asserted low for command/address data to transfer and state to change. 4. taenn must be deasserted high and trdataenn must be asserted low to execute the data phase. 5. next state = 0 if trlastcycn is asserted low (end of target read data). 6. next state = 0 if twlastcycn is asserted low (end of target command/address phase). ta b le 23. quad-port target read 1. when treqn is deasserted high, the target interface is idle. 2. when treqn is asserted low, a command/address phase is in progress. 3. taenn must be asserted low for command/address data to transfer and state to change. 4. taenn must be deasserted high and trdataenn must be asserted low to execute the data phase. 5. next state = 0 if trlastcycn is asserted low (end of target read data). 6. next state = 0 if twlastcycn is asserted low (end of target command/address phase). tstatecntr next state of tstatecntr description data on bus datatofpgax[3:0] datatofpga[31:0] data on bus datafmfpga[31:0] notes 00 idle xxxxxxxx 16 ?1 01 or 0 address[31:0] x 2, burst, dual-address , pciaddress[31:0] pcidata[31:0] 2, 3, 4, 5, 6 10 address[63:32] x 2, burst, dual-address , pciaddress[63:32] pcidata[63:32] 2, 3, 4, 5, 6 tstatecntr next state of tstatecntr description data on bus twdata[17:0] data on bus trdata[15:0] notes 00 idle xx 2 , xxxx 16 ?1 01 or 0 address[15:0] burst, dual-address, pciaddress[15:0] pcidata[15:0] 2, 3, 4, 6 12 or 0 address[31:16] burst, dual-address, pciaddress[31:16] pcidata[31:16] 2, 3, 4, 5, 6 23 or 0 address[47:32] burst, dual-address, pciaddress[47:32] pcidata[47:32] 2, 3, 4, 6 30 address[63:48] burst, dual-address, pciaddress[63:48] pcidata[63:48] 2, 3, 4, 5, 6
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 78 lucent technologies inc. lattice semiconductor pci bus core target controller detailed description (continued) clocking options at fpga/embedded core boundary the or3tp12 pci bus core is divided into two clock domains by two sets of dual-port fifos, one set dedi- cated to each target and master function. the fpga supplies at least one clock, while the pci bus provides the second clock ( clk ). the master and target fifos interface are always independently clocked on the fpga side by either fclk1 or fclk2 . the clocks used for the master fifo and target fifo interfaces to the fpga application can be independent when the interface is con gured in quad-port mode, but they must use the same clock sig- nal for dual-port mode. for dual-port, only one clock port is active while the other is tied inactive. all transfers to/from the fifo interfaces are synchro- nized to fclk1 and/or fclk2 . which port is used for syn- chronization is decided by the fpsc con guration manager for the master and target fifo interfaces. the isplever software will minimize the clock skew between the ffs involved in the data transfers and the appropriate synchronized clock port. the clock delay from the clock source to the fclk1/2 port usually does not affect transfer across the master or target fifo interface, since the interface is referenced from the clock port ( fclk1 or fclk2 ) and not the clock source driver. figure 34 illustrates the special clock paths provided to service the clocking needs of or3tp12. the various clocking options shown in figure 34 are discussed below. pci clock as interface clock the clock received from the pci bus can be brought across the embedded core into the fpga logic section and used as the clock for the entire or3tp12, and ev en as the clock for the entire board on which the or3tp12 resides. it is important that this signal be obtained via the embedded pci bus core only since pci rules allow for one load per agent on the pci bus clock. the or3tp12 incorporates a clock tree for dis- tributing the pci clock; these lines are hard-connected in the pci bus core's circuitry and are passed up onto the fpga portion's clock grid. from there, the clock can feed all pfus, pios, fclk1 , fclk2 , and off-chip resources. local clock as interface clock the fifo interface between the pci bus core and the fpga must use clocks sourced from the fpga array. the master and target fifo interfaces each have inde- pendent clock nets ( fclk1/2 ) and can be connected to the same or separate clocks. both the master and tar- get fifo interface can be independently con gured to use any clock located in the fpga, or provided exter- nally. the clocks for the master and target fifo interface are f ed from speci c vertical clock spines, namely, the spines in plc columns ve and 13. consequently, min- imum clock net delay is obtained by feeding external clocks from i/o pads in locations on the top of the array near these splines. depending on which spline ( fclk1 or fclk2 ) is used to distribute the clock to the master and target fifo interface, it is recommended to use a pio that lies in that same column as the spline. for fclk1 (which lies in column 13), use a pio in pt13a- pt14d. for fclk2 (which lies in column v e), use a pio in pt5a-pt6d. if the user chooses the fast_clock or express_clock as a source for the or3tp12 clock, additional clock delay may be introduced. never- theless, clocks can be fed from any i/o pad, from e xpress clock inputs, or from internal logic, and can be f ed via the pcm.
lucent technologies inc. 79 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core target controller detailed description (continued) 5-7553 (f) figure 34. fpsc block diagram and clock network master read fifo bus mux bus mux target target pci bus master write fifo write fifo read fifo interface logic network network pci clock local clock pci clock local clock fpga pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pfu pci core
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 80 lucent technologies inc. lattice semiconductor pci bus core target controller detailed description (continued) con guration space of the pci bus core the following section describes the con guration space of the pci bus core, as de ned in the pci speci cation and speci c additions to this implementation. note that the term con guration has two meanings: in the fpga con- text, it refers to the programming of the fpga?s resources to de ne its functionality, and in the pci context, it refers to the process of initializing the personality of the pci agent. normally, this agent will reside at a unique location or card slot de ned by a physical address line idsel . the pci?s con guration space is described as follows. pci bus core con guration space organization ta b le 24 shows the layout of the pci bus core?s con guration space. the header type is 00 hex (non-pci-to-pci bridge). all required features and many optional features are implemented. in this implementation, the de ned con- guration space extends beyond 0x3f hex, and includes provisions for hot swap and fpga con guration via the pci bus. table 25 further details the content and function of each register in the pci con guration space. tab le 24. con guration space layout 31 16 15 0 device id vendor id 00h status command 04h class code revision id 08h bist header type latency timer cache line size 0ch base address registers 10h 14h 18h 1ch 20h 24h cardbus cis pointer 28h subsystem id subsystem vendor id 2ch expansion rom base address 30h reserved cap_ptr 34h max_lat min_gnt interrupt pin interrupt line 3ch reserved fpga con guration command-status register 40h fpga con guration data register 44h scratch register 48c reserved 40c reserved hs_csr next item capability id 48h 54h reserved thru ffh
lucent technologies inc. 81 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core target controller detailed description (continued) tab le 25. con guration space assignment 1. these values are intended to be custom assigned, per the intended application, by assigning constants via the fpga con guration manager. 2. these bits exhibit special behavior per the pci speci cation: ? reads behave normally. ? writing a one clears the bit to 0. ? writing a 0 has no effect on the bit. 3. bytes 10?27 hex contain the base address registers (bars). ? any legal combination of memory and i/o bars is permitted, as long as 64-bit bars are naturally aligned, that is, they occupy bytes 10?17, 18?1f, or 20?27 hex. ? memory bars may be marked as prefetchable/nonprefetchable by setting/resetting bit 3; however, the pci bus core?s behavior is not affected by this setting. in particular, the target read operation may discard unused fifo read-ahead data even though the data space is marked as nonprefetchable (this is not a violation since the nonprefetchable bit only says that data can?t be discarded once it has been sent over the pci bus; nevertheless, caution must be exercised when this bit is reset). 4. these signals are tied to the fpga signal of the same name and are not initialized. 5. these bits exhibit special behavior per the compactpci hot swap speci cation: ? reads behave normally. ? writing a one clears the bit to 0. ? writing a 0 has no effect on the bit. 6. this 32-bit register is used during manufacturing test. writes are not allowed; reads are allowed and cause no side effects, b ut the value returned is unde ned. bytes width bit description read/write initial value after fpga con guration 00?01 16 ? vendor id read only 11c1h (lattice) 02?03 16 ? device id read only 5400h (or3tp12) 04?05 16 0 1 2 3 4 5 6 7 8 9 15?10 command: enable i/o space enable memory space enable bus master enable special cycle enable mem wr & inv enable vga palette snoop enable par err response enable stepping enable serrn enable fast back-to-back reserved read/write read/write read/write read only read only read only read/write read only read/write read/write read only 0 0 note 1 0 0 0 0 0 0 0 z eros 06?07 16 3?0 4 5 6 7 8 10?9 11 12 13 14 15 status: reserved capabilities list 66 mhz capable udf supported f ast back-to-back master data parity error devseln timing t arget abort signaled t arget abort received master abort received system error signaled pa r ity error detected read only read only read only read only read only note 2 read only note 2 note 2 note 2 note 2 note 2 z eros 1 1 0 1 0 01b (medium) 0 0 0 0 0
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 82 lucent technologies inc. lattice semiconductor pci bus core target controller detailed description (continued) tab le 25. con guration space assignment (continued) 1. these values are intended to be custom assigned, per the intended application, by assigning constants via the fpga con guration manager. 2. these bits exhibit special behavior per the pci speci cation: ? reads behave normally. ? writing a one clears the bit to 0. ? writing a 0 has no effect on the bit. 3. bytes 10?27 hex contain the base address registers (bars). ? any legal combination of memory and i/o bars is permitted, as long as 64-bit bars are naturally aligned, that is, they occupy bytes 10?17, 18?1f, or 20?27 hex. ? memory bars may be marked as prefetchable/nonprefetchable by setting/resetting bit 3; however, the pci bus core?s behavior is not affected by this setting. in particular, the target read operation may discard unused fifo read-ahead data even though the data space is marked as nonprefetchable (this is not a violation since the nonprefetchable bit only says that data can?t be discarded once it has been sent over the pci bus; nevertheless, caution must be exercised when this bit is reset). 4. these signals are tied to the fpga signal of the same name and are not initialized. 5. these bits exhibit special behavior per the compactpci hot swap speci cation: ? reads behave normally. ? writing a one clears the bit to 0. ? writing a 0 has no effect on the bit. 6. this 32-bit register is used during manufacturing test. writes are not allowed; reads are allowed and cause no side effects, b ut the value returned is unde ned. bytes width bit description read/write initial value after fpga con guration 08 8 ? revision id read only note 1 09?0b 24 ? class code read only note 1 0c 8 ? cache line size read only zeros 0d 8 7?3 2?0 latency timer: programmable portion granularity eight clks read/write read only near 1 z eros 0e 8 ? header type read only 00h 0f 8 ? bist read only zeros 10?27 192 ? base address register note 3 note 1 28?2b 32 ? cardbus cis pointer read only zeros 2c?2d 16 ? subsystem vendor id read only zeros 2e?2f 16 ? subsystem id read only note 1 30?33 32 ? expansion rom base address read only zeros 34 8 ? capabilities pointer read only 50h 35?37 24 ? (reserved) read only zeros 38?3b 32 ? (reserved) read only zeros 3c 9 ? interrupt line read/write zeros 3d 8 ? interrupt pin read only 01h ( intan ) 3e 8 ? min_gnt read only note 1 3f 8 ? max_lat read only note 1
lucent technologies inc. 83 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core target controller detailed description (continued) tab le 25. con guration space assignment (continued) 1. these values are intended to be custom assigned, per the intended application, by assigning constants via the fpga con guration manager. 2. these bits exhibit special behavior per the pci speci cation: ? reads behave normally. ? writing a one clears the bit to 0. ? writing a 0 has no effect on the bit. 3. bytes 10?27 hex contain the base address registers (bars). ? any legal combination of memory and i/o bars is permitted, as long as 64-bit bars are naturally aligned, that is, they occupy bytes 10?17, 18?1f, or 20?27 hex. ? memory bars may be marked as prefetchable/nonprefetchable by setting/resetting bit 3; however, the pci bus core?s behavior is not affected by this setting. in particular, the target read operation may discard unused fifo read-ahead data even though the data space is marked as nonprefetchable (this is not a violation since the nonprefetchable bit only says that data can?t be discarded once it has been sent over the pci bus; nevertheless, caution must be exercised when this bit is reset). 4. these signals are tied to the fpga signal of the same name and are not initialized. 5. these bits exhibit special behavior per the compactpci hot swap speci cation: ? reads behave normally. ? writing a one clears the bit to 0. ? writing a 0 has no effect on the bit. 6. this 32-bit register is used during manufacturing test. writes are not allowed; reads are allowed and cause no side effects, b ut the value returned is unde ned. bytes width bit description read/write initial value 40?41 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fpga con g. command-status register: gsr pci core global set/reset con gfpga enable fpga con g. rdcfgn enable readback prgmn reset fpga con g. logic f astslown fast/slow con g. clock biterr_1 error signal from fpga biterr_0 error signal from fpga ? reserved ? reserved reserved srfull shift reg. full srempty shift reg. empty handshakeerrorshift reg. error initn fpga?s initn done fpga?s done asbmode ready to con g read/write read/write read/write read/write read/write read only read only read only read only read only read only read only read/only read only read only read only 0 0 1 1 0 0 0 0 0 0 0 0 0 note 4 note 4 1 42?43 16 ? (reserved) read only zeros 44?47 32 ? fpga con g. data register read/write zeros 48-4b 32 ? scratch register read/write zeros 4c 32 ? reserved for manufacturing testing note 6 note 6 50 8 ? capability id read only 06h (hot plug) 51 8 ? next item read only 00h (last item) 52 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? hot swap control status register: ins freshly inserted ext pending extraction reserved reserved loo led on/off reserved eim enumn signal mask reserved note 5 note 5 read only read only read/write read only read/write read only 1 0 0 0 0 0 0 0
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 84 lucent technologies inc. lattice semiconductor pci bus core target controller detailed description (continued) fpsc con guration the or3tp12 fpsc provides the designer many fpga con guration options. in addition to all the con- guration options provided in the standard series 3 architecture (except master parallel mode) the or3tp12 pci fpsc can also be con gured via the pci interface. this feature is possible since the pci interface is functional even before the fpsc has been con gured. with this capability, many con guration schemes can be implemented. for example, a generic fpsc con guration can be loaded via a serial con gu- r ation prom and updated via the pci bus or the micro- processor interface. the fpsc can also be reprogrammed in the eld, or the con guration can be dynamically modi ed to perform different tasks. in a proprietary system or using one fpsc, the system software can locate the or3tp12 by reading the ven- dor id and device id. once identi ed, any pci agent can write 32-bit words into the pci con guration regis- ter at address 0x44. this data is then serially shifted into the fpga con guration logic, and distributed to the fpsc programmable resources as if the data was from an external serial prom. when multiple fpscs are con gured via the pci inter- f ace in a standard pci system, there can be an identi - cation issue that must be resolved. the subsystem v endor id and subsystem id that reside at 2ch?2fh in the pci con guration space contains default values after power-up, but before con guration. these identi - cation values are usually needed by system software to identify where an or3tp12 resides on the pci bus, and which fpsc con guration bit stream to use for each or3tp12. therefore, for multiple fpscs being con gured employing the pci interface, each should be initialized via a small serial prom after power-up. this initialization bit stream will contain a unique subsystem and/or subsystem vendor id (de ned by the fpsc con- guration manager) to describe each device operation in the system. for the fpga design in the initialization bit stream, all embedded core input controls signals should be tied to their inactive state, especially t_retryn and t_abort to allow access to the pci con g- uration space. to minimize the size of this initial bit stream, use the options available in bit stream genera- tion process to use explicit addressing, and remove z ero data frames. this initial con guration bit stream is only required to provide correct subsystem vendor id and subsystem id values for system software use, but it may, in addi- tion, be the rst version of the fpsc?s application code. the pci system software is then able to invoke the proper procedures that will recon gure the or3tp12 using the nal version of the application. fpga con guration via pci bus the or3tp12 is con gured using registers located at 0x40 hex and 0x44 hex in the pci con guration space. these registers are dedicated to the or3tp12 con g- uration and readback functions and are detailed in ta b le 25. the fpga con guration control-status regis- ter (fccsr) is a 16-bit register at address 0x40 hex, and the fpga con guration data register (fcdr) is a 32-bit register at address 0x44 hex. the following is an example sequence which con g- ures the or3tp12 via the pci interface: 1. read the vendor id (0x0) and device id (0x0) regis- ters. if the vendor id is 0x11c1 hex, the vendor is lattice. if the device id is 0x5400 hex, the device is a lattice or3tp12 pci fpsc 2. if using an auxiliary initialization device (serial prom, mpi, etc.) for subsystem id identi cation setup, read the fccsr (0x40) until done (bit 1) goes active-high. this indicates that the bit stream f or subsystem id initialization has loaded. 3. read the class code, revision id, subsystem vendor id, and subsystem id registers. this information has been programmed into the fpsc by an initialization bit stream or is the powerup default. it can be used by the con guration software to locate the correct or3tp12 con guration bit stream and driver for the or3tp12s application. 4. read the fccsr (0x40) until asbmode (bit 0) goes active-high, indicating that the jtag controller is not in control of the fpga con guration logic. 5. toggle prgrmn (bit 12) in the fcssr (0x40) low to reset the current the fpga con guration. write to the fccsr (0x40) three times, rst with prgmn high, then active-low, then high. 6. write to the fccsr (0x40) with con gfpga (bit 14) active-high. this will initiate an fpga con guration session via the pci interface. 7. read the fccsr (0x40) until srempty (bit 4) goes active-high, indicating that the con guration shift reg- ister is ready for data. 8. write a 32-bit word of or3tp12 con guration data to the fcdr (0x44), noting that bit 32 will be the rst bit to exit the shift register to the fpga con guration logic.
lucent technologies inc. 85 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pci bus core target controller detailed description (continued) f or example, the con guration header and id frame from an or3tp12 bit stream le are as follows: >11111111111100100000010011011000101100001 1111111 >01011111111111110000000000000000000000000 000000000000000000000001110000000 >0100000101000011111111 this is broken into 32-bit words from left to right, with the left-most bit the msb >11111111111100100000010011011000 = > fff204d8 >10110000111111110101111111111111 = > c0ff5fff therefore, the rst two 32-bit writes into fcdr (0x44) by pci con guration writes would be 0xfff204d8 and 0xc0ff5ff. 9. read the fccsr (0x40) until srempty (bit 4) goes active-high, indicating that the word it con- tained has been transferred to the fpga con gura- tion logic. 10. read the fccsr (0x40) register and verify no errors have occurred. (bit_err = 0 (bit 9), bit_err = 0 (bit 10), and handshake_error = 0 (bit 3), and initn = 1 (bit 2). 11. repeat steps 8, 9, and 10 until all the con guration data has been written. 12. read the fccsr (x40) and verify that done (bit 1) w ent active-high, indicating that the con guration w as successful. readback via pci interface the procedure for performing a readback via the pci interface is similar to the above procedure for con gura- tion. it is also similar to the standard readback proce- dure of series 3 fpga, where the design needs the readback controller present in the design, the appropri- ate bit stream options enabled, and the or3tp12 con- gured. the steps are outlined as follows: 1. read the fccsr (0x40) until asbmode (bit 0) goes active-high, indicating that the jtag controller is not in control of the fpga con guration logic. 2. write to the fccsr (0x40) with rdcfgn (bit 13) active-low, enabling the readback mode. 3. read the fccsr (0x40) until sregfull (bit 5) goes active-high, indicating that a 32-bit word of readback data is available in register fcdr (0x44). 4. read the data from the fcdr (0x44) through a con- guration read. 5. repeat steps 3 and 4 until all readback data has been accessed. f or multiple readbacks, reset the readback mechanism as follows: 1. reset rdcfgn (bit 13) in the fccsr (0x40). 2. set con gfpga (bit 14) in the fccsr (0x40). 3. write the 32-bit word (0xffff_ffff) to the fcdr (0x44). 4. reset con gfpga (bit 14) in the fccsr (0x40). 5. perform readback as described above. interaction among 3tp12 con guration modes the basic fpga con guration options, including con- guration via the microprocessor and boundary-scan interfaces, are performed in a manner identical to that of orca series 3 fpgas. fpsc con guration via the pci interface is available at any time, either prior to or after the fpsc has been con gured and regardless of the value to which the fpga con guration mode pins (m2, m1, and m0) have been strapped. in this priority scheme, a pci directed con guration will ov erride any strapped con guration operation already underway, an fpga con guration via the boundary- scan interface will override one via the pci interface, and the prgm pin overrides both. once a con guration via the pci interface is executed, all options except boundry scan are disabled. to enable the default mode speci ed by the mode pins, assert the reset pin low after toggling the prgrm.
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 86 lucent technologies inc. lattice semiconductor fpga con guration target controller data format the isplever development system interfaces with front-end design entry tools and provides tools to pro- duce a fully con gured fpsc. this section discusses using the isplever development system to generate con guration ram data and then provides the details of the con guration frame format. using isplever to generate con guration ram data the con guration data bit stream de nes the pci embedded core con guration, the fpga logic function- ality, and the i/o con guration and interconnection. the data bit stream is generated by the isplever develop- ment tools. the bit stream created by the bit stream generation tool is a series of ones and 0s used to write the fpsc con guration ram. it can be loaded into the fpsc using one of the con guration modes discussed elsewhere in this data sheet. f or fpscs, the bit stream is prepared in two separate steps in the design o w. the con guration options of the embedded core are speci ed using orca or3tp12 design kit software at the beginning of the design process. this offers the designer a speci c con- guration to simulate and design the fpga logic to. upon completion of the design, the bit stream genera- tor combines the embedded core options and the fpga con guration into a single bit stream for down- load into the fpsc. fpga con guration data frame con guration data can be presented to the fpsc in two frame formats: autoincrement and explicit. a detailed description of the frame formats are shown in figure 35, figure 36, and table 26. the two modes are similar except that autoincrement mode uses assumed address incrementation to reduce the bit stream size, and explicit mode requires an address for each data frame. in both cases, the header frame begins with a series of ones and a preamble of 0010, followed by a 24-bit length count eld representing the total number of con guration clocks needed to complete the loading of the fpsc. the mandatory id frame contains data used to deter- mine if the bit stream is being loaded to the correct type of orca device (i.e., a bit stream generated for an or3tp12 is being sent to an or3tp12). error check- ing is always enabled for series 3+ devices, through the use of an 8-bit checksum. one bit in the id frame also selects between the autoincrement and explicit address modes for this load of the con guration data. a con guration data frame follows the id frame. a data frame starts with a 01-start bit pair and ends with enough 1-stop bits to reach a byte boundary. if using autoincrement con guration mode, subsequent data frames can follow. if using explicit mode, one or more address frames must follow each data frame, telling the fpsc at what addresses the preceding data frame is to be stored (each data frame can be sent to multiple addresses). f ollowing all data and address frames is the postam- bl e. the format of the postamble is the same as an address frame with the highest possible address value with the checksum set to all ones.
lucent technologies inc. 87 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor fpga con guration target controller data format (continued) figure 35. serial con guration data format?autoincrement mode figure 36. serial con guration data format?explicit mode tab le 26. con guration frame format and contents note: for slave parallel mode, the byte containing the preamble must be 11110010. the number of leading header dummy bits must be ( n * 8) + 4, where n is any nonnegative integer and the number of trailing dummy bits must be ( n * 8), where n is any positive integer. the number of stop bits/frame for slave parallel mode must be ( x * 8), where x is a positive integer. note also that the bit stream generator tool supplies a bit stream that is compatible with all con guration modes, including slave parallel mode. header 11110010 preamble. 24-bit length count con guration frame length. 11111111 trailing header?eight bits. id frame 0101 1111 1111 1111 id frame header. con guration mode 00 = autoincrement, 01 = explicit. reserved [41:0] reserved bits set to 0. id 20-bit part id. checksum 8-bit checksum. 11111111 eight stop bits (high) to separate frames. con guration data frame (repeated for each data frame) 01 data frame header. data bits number of data bits depends upon device. alignment bits = 0 string of 0 bits added to bit stream to make frame header, plus data bits reach a byte boundary. checksum 8-bit checksum. 11111111 eight stop bits (high) to separate frames. con guration address frame 00 address frame header. 14 address bits 14-bit address of location to start data storage. checksum 8-bit checksum. 11111111 eight stop bits (high) to separate frames. p ostamble 00 postamble header. 11111111 111111 dummy address. 1111111111111111 16 stop bits. 5-5759(f) configuration data configuration data 10 01 01 preamble length id frame configuration configuration postamble configuration header 00 00 count data frame 1 data frame 2 5-5760(f) preamble length id frame configuration configuration postamble configuration header address address 00 count data frame 1 data frame 2 frame 2 frame 1 configuration data configuration data 10 01 01 00 00 00
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 88 lucent technologies inc. lattice semiconductor fpga con guration target controller data format (continued) the length and number of data frames and information on the prom size for the or3tp12 is given in ta b le 27. tab le 27. con guration frame size bit stream error checking there are three different types of bit stream error checking performed in the orca series 3+ fpscs: id frame, frame alignment, and crc checking. the id data frame is sent to a dedicated location in the fpsc. this id frame contains a unique code for the device for which it was generated. this device code is compared to the internal code of the fpsc. any differ- ences are agged as an id error. this frame is auto- matically created by the bit stream generation program in isplever . each data and address frame in the fpsc begins with a frame start pair of bits and ends with eight stop bits set to one. if any of the previous stop bits were a 0 when a frame start pair is encountered, it is agged as a frame alignment error. error checking is also done on the fpsc for each frame by means of a checksum byte. if an error is f ound on evaluation of the checksum byte, then a checksum/parity error is agged. when any of the three possible errors occur, the fpsc is forced into an idle state, forcing init low. the fpsc will remain in this state until either the reset or prgm pins are asserted. if using either of the mpi modes or the pci embedded core to con gure the fpsc, the speci c type of bit stream error is written to one of the mpi registers or a pci register, respectively, by the fpga con guration logic. the pgrm bit of the mpi control register or the pci embedded core can also be used to reset out of the error condition and restart con guration. fpga con guration modes there are eight methods for con guring the fpsc. six of the con guration modes are selected on the m0, m1, and m2 input and are shown in table 28. the seventh mode is pci bus con guration as previously discussed, and the eighth con guration mode is accessed through the boundary-scan interface. a fourth input, m3, is used to select the frequency of the internal oscillator, which is the source for cclk in some con guration modes. the nominal frequencies of the internal oscilla- tor are 1.25 mhz and 10 mhz. the 1.25 mhz frequency is selected when the m3 input is unconnected or driven to a high state. note that the master parallel mode of con guration that is available in the orca series 3 fpgas is not avail- able in the or3tp12. this is due to the use of master parallel con guration pins for the pci bus interface. more information on the general fpga modes of con- guration can be found in the orca series 3 data sheet. tab le 28. con guration modes * motorola is a registered trademark of motorola, inc. ? intel is a registered trademark of intel corporation. devices or3tp12 number of frames 1240 data bits/frame 232 con guration data (number of frames number of data bits/frame) 287,680 maximum total number bits/frame (align bits, 01 frame start, 8-bit check- sum, eight stop bits) 256 maximum con guration data (number bits/frame number of frames) 317,440 maximum prom size (bits) (add con guration header and postamble) 317,608 m2 m1 m0 cclk con guration mode data 000 output master serial serial 001 input slave parallel parallel 010 output microprocessor: motorola * po w erpc pa r allel 011 output microprocessor: intel ? i960 pa r allel 100 reserved 101 output async peripheral parallel 110 reserved 111 input slave serial serial
lucent technologies inc. 89 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. the orca series 3+ fpscs include circuitry designed to protect the chips from damaging substrate injection cur- rents and to prevent accumulations of static charge. nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress. ta b le 29. absolute maximum ratings *f or pci bus signals used for 5 v signaling and fpga inputs used as 5 v tolerant, the maximum value is 5.8 v. recommended operating conditions ta b le 30. recommend operating conditions note: the maximum recommended junction temperature (t j ) during operation is 125 c. p arameter symbol min max unit storage temperature t stg ?65 150 c supply voltage with respect to ground v dd ?0.5 7.0 v input signal with respect to ground ? ?0.5 v dd + 0.3* v signal applied to high-impedance output ? ?0.5 v dd + 0.3* v maximum package body temperature ? ? 220 c mode or3tp12 t emperature range (ambient) supply voltage (v dd ) commercial 0 c to 70 c 3.0 v to 3.6 v industrial ?40 c to +85 c 3.0 v to 3.6 v
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 90 lucent technologies inc. lattice semiconductor electrical characteristics ta b le 31. electrical characteristics or3tp12 commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c; industrial: v dd = 3.0 v to 3.6 v, ?40 c < t a < +85 c. * on the series 3 devices, the pull-up resistor will externally pull the pin to a level 1.0 v below v dd . p arameter symbol test conditions or3tp12 unit min max input voltage: high low v ih v il input con gured as cmos (clamped to v dd ) 50% v dd gnd ? 0.5 v dd + 0.3 30% v dd v v input voltage: high low v ih v il input con gured as 5 v tolerant 50% v dd gnd ? 0.5 5.8 v 30% v dd v v output voltage: high low v oh v ol v dd = min, i oh = 6 ma or 3 ma v dd = min, i ol = 12 ma or 6 ma 2.4 ? ? 0.4 v v input leakage current i l v dd = max, v in = v ss or v dd ?10 10 a standby current i ddsb (t a = 25 c, v dd = 3.3 v) internal oscillator running, no output loads, inputs at v dd or gnd (after con guration) ? 5.3 ma standby current i ddsb (t a = 25 c, v dd = 3.3 v) internal oscillator stopped, no output loads, inputs at v dd or gnd (after con guration) ? 1.4 ma data retention voltage v dr t a = 25 c 2.3 ? v po we r up current i pp po w er supply current at approximately 1 v, within a recommended power supply ramp rate of 1 ms?200 ms 2.7 ? ma input capacitance c in (t a = 25 c, v dd = 3.3 v) test frequency = 1 mhz ?8pf output capacitance c out (t a = 25 c, v dd = 3.3 v) test frequency = 1 mhz ?9pf done pull-up resistor* r done ? 100 ? kw m[3:0] pull-up resistors* r m ? 100 ? kw i/o pad static pull-up current* i pu (v dd = 3.6 v, v in = v ss , t a = 0 c) 14.4 50.9 a i/o pad static pull-down current i pd (v dd = 3.6 v, v in = v ss , t a = 0 c) 26 103 a i/o pad pull-up resistor* r pu v dd = all, v in = v ss , t a = 0 c 100 ? kw i/o pad pull-down resistor r pd v dd = all, v in = v dd , t a = 0 c 50 ? kw
lucent technologies inc. 91 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor timing characteristics description the most accurate timing characteristics are reported by the timing analyzer in the isplever development system. a timing report provided by the development system after layout divides path delays into logic and routing delays. the timing analyzer can also provide logic delays prior to layout. while this allows routing b udget estimates, there is wide variance in routing delays associated with different layouts. the logic timing parameters noted in the electrical characteristics section of this data sheet are the same as those in the design tools. in the pfu timing, symbol names are generally a concatenation of the pfu oper- ating mode and the parameter type. the setup, hold, and propagation delay parameters, de ned below, are designated in the symbol name by the set, hld, and del characters, respectively. the values given for the parameters are the same as those used during production testing and speed bin- ning of the devices. the junction temperature and sup- ply voltage used to characterize the devices are listed in the delay tables. actual delays at nominal tempera- ture and voltage for best-case processes can be much better than the values given. it should be noted that the junction temperature used in the tables is generally 85 c. the junction temperature f or the fpga depends on the power dissipated by the device, the package thermal characteristics ( ja ), and the ambient temperature, as calculated in the following equation and as discussed further in the package thermal characteristics section: t jmax = t amax + (p ? ja ) c note : the user must determine this junction tempera- ture to see if the delays from isplever should be derated based on the following derating tables. ta b le 32 and table 33 provide approximate power sup- ply and junction temperature derating for or3tp12 commercial devices. the delay values in this data sheet and reported by isplever are shown as 1.00 in the tables. the method for determining the maximum junction temperature is de ned in the package thermal characteristics section. taken cumulatively, the range of parameter values for best-case vs worst-case pro- cessing, supply voltage, and junction temperature can approach three to one. ta b le 32. derating for commercial devices ( i/o supply v dd ) note: the derating tables shown above are for a typical critical path that contains 33% logic delay and 66% routing delay. since the routing delay derates at a higher rate than the logic delay, paths with more than 66% routing delay will derate at a higher r ate than shown in the table. the approximate derating values vs temperature are 0.26% per c for logic delay and 0.45% per c for routing delay. the approximate derating values vs v oltage are 0.13% per mv for both logic and routing delays at 25 c. propagation delay . the time between the speci ed reference points. the delays provided are the worst case of the tphh and tpll delays for noninverting func- tions, tplh and tphl for inverting functions, and tphz and tplz for 3-state enable. setup time . the interval immediately preceding the transition of a clock or latch enable signal, during which the data must be stable to ensure it is recognized as the intended value. hold time . the interval immediately following the tran- sition of a clock or latch enable signal, during which the data must be held stable to ensure it is recognized as the intended value. 3-state enable . the time from when a 3-state control signal becomes active and the output pad reaches the high-impedance state. t j ( c ) po wer supply voltage 3.0 v 3.3 v 3.6 v ?40 0.82 0.72 0.66 0 0.91 0.80 0.72 25 0.98 0.85 0.77 85 1.00 0.99 0.90 100 1.23 1.07 0.94 125 1.34 1.15 1.01
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 92 lucent technologies inc. lattice semiconductor timing characteristics (continued) pfu timing refer to orca or3c/txxx series data sheet for the f ollowing: combinational pfu timing characteristics sequential pfu timing characteristics ripple mode pfu timing characteristics synchronous memory write characteristics synchronous memory read characteristics plc timing refer to orca or3c/txxx series data sheet for the f ollowing: pfu output mux and direct routing timing charac- teristics slic timing refer to orca or3c/txxx series data sheet for the f ollowing: supplemental logic and interconnect cell (slic) timing characteristics pio timing refer to orca or3c/txxx series data sheet for the f ollowing: programmable i/o (pio) timing characteristics special function timing refer to orca or3c/txxx series data sheet for the f ollowing: microprocessor interface (mpi) timing characteris- tics programmable clock manager (pcm) timing char- acteristics boundary-scan timing characteristics clock timing refer to orca or3c/txxx series data sheet for the f ollowing: expressclk (eclk) and fast clock (fclk) timing characteristics general-purpose clock timing characteristics (internally generated clock) or3tp12 expressclk to output delay (pin-to-pin) or3tp12 fast clock (fclk) to output delay (pin- to-pin) or3tp12 general system clock (sclk) to output delay (pin-to-pin) or3tp12 input to expressclk (eclk) fast capture set-up/hold time (pin-to-pin) or3tp12 input to fast clock setup/hold time (pin- to-pin) or3tp12 input to general system clock setup/hold time (pin-to-pin) con guration timing refer to orca or3c/txxx series data sheet for the f ollowing: general con guration mode timing characteristics master serial con guration mode timing character- istics asynchronous peripheral con guration mode timing characteristics slave serial con guration mode timing characteris- tics microprocessor interface timing characteristics readback timing refer to orca or3c/txxx series data sheet for the f ollowing: readback timing characteristics
lucent technologies inc. 93 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor timing characteristics (continued) ta b le 33. or3tp12 pci and fpga interface clock operation frequencies or3tp12 commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c. * the pci clock frequency is based on the internal register to register frequency and the 66 mhz pci i/o speci cations. ? the maximum user interface clock frequencies are values based on registering all signals at the fpga/asic boundary. this numbe r will be lower depending on the design implementation and number of fpga logic levels into and out of the asic. ? this is the typical operating frequency for a real design that does not register signals at the fpga/asic boundary. ta b le 34. or3tp12 fpga to pci, and pci to fpga, combinatorial path delays or3tp12 commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c. notes: on the fpga to pci combinatorial path delays, they include the asic path delay and the output buffer delay under a 10pf load. they do not include the interbuf delay on the fpga side. on the pci to fpga combinatorial path delays, they include the asic input buffer delay, and asic path delay entering the fpga. they do not include the interbuf delay on the fpga side. description (t i = 85 c, v dd = min, v dd 2 = min) speed ?7 unit signal min typ max clk (pci clock) 0 ?* 66* mhz fclk1 (user interface clock) 0 ? ? 66 ? mhz fclk2 (user interface clock) 0 ? ? 66 ? mhz description (t i = 85 c, v dd = min, v dd 2 = min) min max unit source destination pci_intan (fpga side) intan (pci side) ? 4.601 ns clk (pci side) pciclk (fpga side) ? 4.544 ns r stn (pci side) pci_rstn (fpga side) ? 2.442 ns
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 94 lucent technologies inc. lattice semiconductor timing characteristics (continued) ta b le 35. or3tp12 fpga side interface combinatorial path delay signals or3tp12 commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c. note: the combinatorial path parameters are measured from the input to the output (both on the fpga side), excluding the interb ufs, which traverse the asic/fpga boundary. the isplever static analysis tool, trace, accounts for clock skew and interbuf delays on the clock and data paths. ta b le 36. or3tp12 interbuf delays or3tp12 commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c. note: the interbufs are buffers that interface between the fpga and the asic. description (t i = 85 c, v dd = min, v dd 2 = min) min max unit source destination f o_sel datatofpga[31:0] ? 2.364 ns f o_sel datatofpgax[3:0] ? 1.999 ns twdataenn twlastcycn ? 6.565 ns twdataenn datatofpga[31:0] (dual-port mode) ? 8.968 ns twdataenn datatofpgax[3:0] (dual-port mode) ? 7.929 ns twdataenn twdata[17:0] (quad-port mode) ? 7.687 ns trdataenn trlastcycn ? 5.457 ns mrdataenn mrlastcycn ? 5.899 ns taenn twlastcycn ? 6.530 ns taenn datatofpga[31:0] (dual-port mode) ? 9.278 ns taenn datatofpgax[3:0] (dual-port mode) ? 7.904 ns taenn twdata[17:0] (quad-port mode) ? 7.696 ns cfgshiftenn pci_cfg_stat ? 6.202 ns mrdataenn datatofpga[31:0] ? 7.516 ns mrdataenn mrdata[17:0] ? 7.340 ns description (t i = 85 c, v dd = min, v dd 2 = min) min max unit interbuf from fpga to asic ? 0.696 ns interbuf from asic to fpga ? 0.505 ns
lucent technologies inc. 95 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor timing characteristics (continued) ta b le 37. or3tp12 fpga side interface clock to output delays, pciclk synchronous signals or3tp12 commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c. note: the clock to out parameters are measured from the pciclk clock output pin on the fpga side, excluding the interbufs, which traverse the asic/fpga boundary. the isplever static analysis tool, trace, accounts for clock skew and interbuf delays on the clock and data paths. ta b le 38. or3tp12 fpga side interface clock to output delays, fclk synchronous signals or3tp12 commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c. note: the clock to out parameters are measured from the fclk1 and fclk2 clock input pins on the fpga side, excluding the interbufs, which traverse the asic/fpga boundary. the isplever static analysis tool, trace, accounts for clock skew and interbuf delays on the clock and data paths. description (t i = 85 c, v dd = min, v dd 2 = min) min max unit tcmd[3:0] ? 5.124 ns bar[2:0] ? 4.586 ns pci_cfg_stat ? 11.383 ns description (ti = 85 c, v dd = min, v dd 2 = min) min max unit fpga_msyserror ? 3.468 ns ma_fulln ? 4.230 ns mstatecntr[3:0] ? 5.049 ns m_ready ? 4.996 ns mw_fulln ? 4.918 ns mw_afulln ? 4.056 ns datatofpga[31:0] (dual-port mode) ? 12.514 ns datatofpgax[3:0] (dual-port mode) ? 11.347 ns mrdata[17:0] (quad-port mode) ? 12.514 ns twdata[17:0] (quad-port mode) ? 11.229 ns mr_emptyn ? 4.302 ns mr_aemptyn ? 4.169 ns mrlastcycn ? 8.835 ns disctimerexpn ? 3.673 ns treqn ? 5.643 ns t_ready ? 4.779 ns tstatecntr[3:0] ? 5.716 ns tw_emptyn ? 4.741 ns tw_aemptyn ? 4.360 ns twlastcycn ? 10.212 ns tr_fulln ? 4.554 ns tr_afulln ? 4.216 ns trlastcycn ? 6.154 ns
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 96 lucent technologies inc. lattice semiconductor timing characteristics (continued) ta b le 39. or3tp12 fpga side interface input setup delays, pciclk synchronous signals or3tp12 commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c. note: the input setup parameters are measured from the pciclk clock output pin on the fpga side, excluding the interbufs, which traverse the asic/fpga boundary. the isplever static analysis tool, trace, accounts for clock skew and interbuf delays on the clock and data paths. ta b le 40. or3tp12 fpga side interface input setup delays, fclk synchronous signals or3tp12 commercial: v dd = 3.0 v to 3.6 v, 0 c < t a < 70 c. note: the input setup parameters are measured from the fclk1 and fclk2 clock input pins on the fpga side, excluding the interbufs, which traverse the asic/fpga boundary. the isplever static analysis tool, trace, accounts for clock skew and interbuf delays on the clock and data paths. description (ti = 85 c, v dd = min, v dd 2 = min) min max unit fpga_mbusyn 0? ns deltrn 0? ns mwpcihold 3.943 ? ns mr_mstopburstn 0? ns t_abort 1.197 ? ns t_retryn 0.795 ? ns twburstpendn 0? ns trpcihold 0.693 ? ns trburstpendn 0? ns fpga_syserror 0? ns cfgshiftenn 0? ns description (ti = 85 c, v dd = min, v dd 2 = min) min max unit maenn 6.426 ? ns mwdataenn 6.452 ? ns datafmfpga[31:0] (dual-port mode) 7.344 ? ns datafmfpgax[3:0] (dual-port mode) 5.226 ? ns mwdata[17:0] (quad-port mode) 7.205 ? ns trdata[17:0] (quad-port mode) 7.344 ? ns mwlastcycn 6.680 ? ns mrdataenn 5.371 ? ns taenn 5.048 ? ns twdataenn 5.099 ? ns trdataenn 5.919 ? ns
lucent technologies inc. 97 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor input/output buffer measurement conditions note: switch to v dd for t plz /t pzl ; s witch to gnd for t phz /t pzh . figure 37. ac test loads figure 38. output buffer delays figure 39. input buffer delays 5-3234(f) 50 pf a. load used to measure propagation delay to the output under test to the output under test 50 pf v cc gnd 1 k ? b. load used to measure rising/falling edges 5-3233.a(f) v dd t phh v dd /2 v ss out[i] pa d out 1.5 v 0.0 v t pll pad out[i] ac test loads (shown above) ts[i] out 5-3235(f) 0.0 v 1.5 v t phh t pll pa d in[i] in 3.0 v v ss v dd /2 v dd p ad in in[i]
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 98 lucent technologies inc. lattice semiconductor output buffer characteristics 5-6865(f) figure 40. sinklim (t j = 25 c, v dd = 3.3 v) 5-6867(f) figure 41. slewlim (t j = 25 c, v dd = 3.3 v) 5-6867(f) figure 42. fast (t j = 25 c, v dd = 3.3 v) 5-6866(f) figure 43. sinklim (t j = 125 c, v dd = 3.0 v) 5-6868(f) figure 44. slewlim (t j = 125 c, v dd = 3.0 v) 5-6868(f) figure 45. fast (t j = 125 c, v dd = 3.0 v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 20 40 60 110 output volta ge , v o (v) i ol 70 50 30 10 i oh output current, i o (ma) 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 40 80 output voltage, v o (v) i ol 100 60 20 i oh output current, i o (ma) 120 140 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 40 80 output voltage, v o (v) i ol 100 60 20 i oh output current, i o (ma) 120 140 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 20 40 60 output voltage, v o (v) i ol 70 50 30 10 i oh output current, i o (ma) 80 90 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 40 80 output voltage, v o (v) i ol 100 60 20 i oh output current, i o (ma) 120 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 40 80 output voltage, v o (v) i ol 100 60 20 i oh output current, i o (ma) 120
lucent technologies inc. 99 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor estimating power dissipation the total power dissipated by the or3tp12 is the combined power dissipated by the pci bus core and fpga array. the maximum power dissipated will not exceed that of its base array the or3t55 fpga. the maximum power used by the pci bus core will be 890 mw at 66 mhz, 3.6 v and 85 c. general fpga power estimation parameters can be found in the orca series 3 data sheet.
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 100 lucent technologies inc. lattice semiconductor symbol i/o description dedicated pins v dd ?p ositive power supply. gnd ? ground supply. reset i during con guration, reset forces the restart of con guration and a pull-up is enabled. after con guration, reset can be used as an fpga logic direct input, which causes all plc latches/ffs to be asynchronously set/reset. cclk i in the master and asynchronous peripheral modes, cclk is an output which strobes con guration data in. in the slave or synchronous peripheral mode, cclk is input synchronous with the data on din or d[7:0]. in microprocessor and pci modes, cclk is used internally and output for daisy-chain operation. done i o as an input, a low level on done delays fpga start-up after con guration.* as an active-high, open-drain output, a high level on this signal indicates that con g- uration is complete. done is also used in the embedded pci core start-up sequence. done has an optional pull-up resistor. prgm i prgm is an active-low input that forces the restart of con guration and resets the boundary-scan circuitry. this pin always has an active pull-up. rd_cfg i this pin must be held high during device initialization until the init pin goes high. this pin always has an active pull-up. during con guration, rd_cfg is an active-low input that activates the ts_all function and 3-states all of the i/o. after con guration, rd_cfg can be selected (via a bit stream option) to activate the ts_all function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on rd_cfg will initiate readback of the con guration data, including pfu output states, starting with frame address 0. rd_data/tdo o rd_data/tdo is a dual-function pin. if used for readback, rd_data provides con- guration data out. if used in boundary scan, tdo is test data out. special-purpose pins m0, m1, m2 i i/o during powerup and initialization, m0?m2 are used to select the con guration mode with their values latched on the rising edge of init ; see table 28 for the con- guration modes. during con guration, a pull-up is enabled. after con guration, m2 can be a user-programmable i/o.* m3 i i/o during powerup and initialization, m3 is used to select the speed of the internal oscillator during con guration with their values latched on the rising edge of init . when m3 is low, the oscillator frequency is 10 mhz. when m3 is high, the oscillator is 1.25 mhz. during con guration, a pull-up is enabled. after con guration, m2 can be a user-programmable i/o pin.* * the orca series 3 fpga data sheet contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con guration pins (and the activation of all user i/os) is controlled by a second set of options. pin information this section describes the pins and signals that perform fpga-related functions. any pins not described in table 5 or here in table 41 are user-programmable i/os. during con guration, the user-programmable i/os are 3-stated and pulled-up with an internal resistor. if any fpga function pin is not used (or not bonded to package pin), it is also 3-stated and pulled-up after con guration. ta b le 41. fpga common-function pin descriptions
lucent technologies inc. 101 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor ** the orca series 3 fpga data sheet contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con guration pins (and the activation of all user i/os) is controlled by a second set of options. symbol i/o description special-purpose pins (continued) tdi, tck, tms i i/o if boundary scan is used, these pins are test data in, test clock, and test mode select inputs. if boundary scan is not selected, all boundary-scan functions are inhibited once con guration is complete. even if boundary scan is not used, either tck or tms must be held at logic one during con guration. each pin has a pull-up enabled during con guration. after con guration, these pins are user-programmable i/o.* rdy/rclk/ mpi_ale o o i i/o during con guration in peripheral mode, rdy/rclk indicates another byte can be written to the fpga. if a read operation is done when the device is selected, the same status is also available on d7 in asynchronous peripheral mode. during the master parallel con guration mode, rclk is a read output signal to an e xternal memory. this output is not normally used. in i960 microprocessor mode, this pin acts as the address latch enable (ale) input. after con guration, if the mpi is not used, this pin is a user-programmable i/o pin.* hdc o high during con guration is output high until con guration is complete. it is used as a control output indicating that con guration is not complete. ldc ol ow during con guration is output low until con guration is complete. it is used as a control output indicating that con guration is not complete. init i/o init is a bidirectional signal before and during con guration. during con guration, a pull-up is enabled, but an external pull-up resistor is recommended. as an active-low open-drain output, init is held low during power stabilization and internal clearing of memory. as an active-low input, init holds the fpga in the wait-state before the start of con guration. cs0 , cs1 i i/o cs0 and cs1 are used in the asynchronous peripheral, slave parallel, and micropro- cessor con guration modes. the fpga is selected when cs0 is low and cs1 is high. during con guration, a pull-up is enabled. after con guration, these pins are user-programmable i/o pins.* rd /mpi_strb i i i/o rd is used in the asynchronous peripheral con guration mode. a low on rd changes d7 into a status output. as a status indication, a high indicates ready, and a low indicates busy. wr and rd should not be used simultaneously. if they are, the write strobe overrides. this pin is also used as the microprocessor interface (mpi) data transfer strobe. for po w erpc , it is the transfer start (ts). for i960 , it is the address/data strobe ( ads ). after con guration, if the mpi is not used, this pin is a user-programmable i/o pin.* wr i i/o wr is used in the asynchronous peripheral con guration mode. when the fpga is selected, a low on the write strobe, wr , loads the data on d[7:0] inputs into an internal data buffer. wr and rd should not be used simultaneously. if they are, the write strobe overrides. after con guration, this pin is a user-programmable i/o pin.* pin information (continued) ta b le 41. fpga common-function pin descriptions (continued)
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 102 lucent technologies inc. lattice semiconductor symbol i/o description special-purpose pins (continued) mpi_irq o i/o mpi active-low interrupt request output. if the mpi is not in use, this is a user-programmable i/o. mpi_bi o i/o po w erpc mode mpi burst inhibit output. if the mpi is not in use, this is a user-programmable i/o. mpi_a ck o in po w erpc mode mpi operation, this is the active-high transfer acknowledge (t a ) out- put. for i960 mpi operation, it is the active-low ready/record (rd yrcv ) output. if the mpi is not in use, this is a user-programmable i/o. mpi_rw i i/o in po w erpc mode mpi operation, this is the active-low write/ active-high read control signals. for i960 operation, it is the active-high write/active-low read control signal. if the mpi is not in use, this is a user-programmable i/o. mpi_clk i i/o this is the clock used for the synchronous mpi interface. for po w erpc , it is the clk- out signal. for i960 , it is the system clock that is chosen for the i960 e xternal bus inter- f ace. if the mpi is not in use, this is a user-programmable i/o. a[4:0] i i/o f or po w erpc operation, these are the po w erpc address inputs. the address bit map- ping (in po w erpc /fpga notation) is a[31]/a[0], a[30]/a[1], a[29]/a[2], a[28]/a[3], a[27]/ a[4]. note that a[27]/a[4] is the msb of the address. the a[4:2] inputs are not used in i960 mpi mode. if the mpi is not in use, this is a user-programmable i/o. a[1:0]/mpi_be[1:0] i f or i960 operation, mpi_be[1:0] provide the i960 byte enable signals, be[1:0] , that are used as address bits a[1:0] in i960 byte-wide operation. d[7:0] i i/o during master parallel, peripheral, and slave parallel con guration modes, d[7:0] receive con guration data, and each pin has a pull-up enabled. during serial con gura- tion modes, d0 is the din input. d[7:0] are also the data pins for po w erpc microproces- sor mode and the address/data pins for i960 microprocessor mode. after con guration, the pins are user-programmable i/o pins.* din i i/o during slave serial or master serial con guration modes, din accepts serial con gura- tion data synchronous with cclk. during parallel con guration modes, din is the d0 input. during con guration, a pull-up is enabled. after con guration, this pin is a user-programmable i/o pin.* dout o i/o during con guration, dout is the serial data output that can drive the din of daisy- chained slave lca devices. data out on dout changes on the falling edge of cclk. after con guration, dout is a user-programmable i/o pin.* * the orca series 3 fpga data sheet contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con guration pins (and the activation of all user i/os) is controlled by a second set of options. pin information (continued) ta b le 41. fpga common-function pin descriptions (continued)
lucent technologies inc. 103 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pin information (continued) ta b le 42. or3tp12 256-pin pbga pinout pin or3tp12 function b1 v dd v dd c2 pl1d i/o d2 pl1c i/o d3 pl1b i/o e4 pl2d i/o-a0/mpi_be0 c1 pl2c i/o d1 pl2b i/o e3 pl2a i/o e2 pl3d i/o e1 pl3a i/o f3 pl4d i/o g4 pl4a i/o-a1/mpi_be1 f2 pl5d i/o f1 pl5a i/o-a2 g3 pl6d i/o g2 pl6b i/o g1 pl6a i/o-a3 h3 pl7d i/o h2 pl7c i/o h1 pl7b i/o j4 pl7a i/o-a4 j3 pl8d i/o-a5 j2 pl8c i/o j1 pl8b i/o k2 pl8a i/o-a6 k3 peckl i-eckl k1 pl9c i/o l1 pl9b i/o l2 pl9a i/o-a7/mpi_clk l3 pl10d i/o l4 pl10c i/o m1 pl10b i/o m2 pl10a i/o-a8/mpi_rw m3 pl11d i/o-a9/mpi_a ck m4 pl11c i/o n1 pl11b i/o pin or3tp12 function n2 pl11a i/o-a10/mpi_bi n3 pl12d i/o p1 pl12c i/o p2 pl12b i/o r1 pl12a i/o-a11/mpi-irq p3 pl13d i/o-a12 r2 pl13b i/o-seckll t1 pl14d i/o p4 pl14b i/o-a13 r3 pl14a i/o t2 pl15d gntn (pci) u1 pl15b reqn (pci) t3 pl16d ad31 (pci) u2 pl17d nc v1 pl17c nc t4 pl17b nc u3 pl17a ad30 (pci) v2 pl18d nc w1 pl18c ad29 (pci) v3 pl18b nc w2 pl18a ad28 (pci) y1 cclk cclk w3 ? nc y2 pb1a r stn (pci) w4 pb1c nc v4 pb1d intan (pci) u5 pb2a vio (pci) y3 pb2b nc y4 pb2c nc v5 pb2d ad27 (pci) w5 pb3d ad26 (pci) y5 pb4d ad25 (pci) v6 pb5a ad24 (pci) u7 pb5b idsel (pci) w6 pb5d ad23 (pci) y6 pb6a ad22 (pci)
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 104 lucent technologies inc. lattice semiconductor pin information (continued) ta b le 43. or3tp12 256-pin pbga pinout (continued) pin or3tp12 function v7 pb6b ad21 (pci) w7 pb6d ad20 (pci) y7 pb7a ad19 (pci) v8 pb7b ad18 (pci) w8 pb7c ad17 (pci) y8 pb7d ad16 (pci) u9 pb8a c_ben3 (pci) v9 pb8b c_ben2 (pci) w9 pb8c trdyn (pci) y9 pb8d nc w10 pb9a nc v10 pb9b irdyn (pci) y10 pb9c devseln (pci) y11 pb9d stopn (pci) w11 peckb c lk (pci) v11 pb10b framen (pci) u11 pb10c perrn (pci) y12 pb10d serrn (pci) w12 pb11a nc v12 pb11b par (pci) u12 pb11c c_ben1 (pci) y13 pb11d c_ben0 (pci) w13 pb12a hdc v13 pb12b ad15 (pci) y14 pb12c ad14 (pci) w14 pb12d ad13 (pci) y15 pb13a ldc v14 pb13b nc w15 pb13c nc y16 pb13d ad12 (pci) u14 pb14a ad11 (pci) v15 pb14d ad10 (pci) w16 pb15a init y17 pb15d ad9 (pci) v16 pb16a nc pin or3tp12 function w17 pb16d ad8 (pci) y18 pb17a ad7 (pci) u16 pb17c nc v17 pb17d ad6 (pci) w18 pb18a ad5 (pci) y19 pb18b nc v18 pb18c nc w19 pb18d ad4 (pci) y20 done done w20 resetn reset v19 prgmn prgm u19 pr18a m0 u18 pr18c enumn (pci) t17 pr18d ledn (pci) v20 pr17a nc u20 pr17b ad3 (pci) t18 pr17c nc t19 pr17d nc t20 pr16a ad2 (pci) r18 pr16d ad1 (pci) p17 pr15a ad0 (pci) r19 pr15c ejectsw (pci) r20 pr15d m1 p18 pr14a i/o p19 pr14d i/o p20 pr13a i/o n18 pr12a i/o-m2 n19 pr12b i/o n20 pr12c i/o m17 pr12d i/o m18 pr11a i/o-m3 m19 pr11b i/o m20 pr11c i/o l19 pr11d i/o l18 pr10a i/o
lucent technologies inc. 105 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pin information (continued) ta b le 43. or3tp12 256-pin pbga pinout (continued) pin or3tp12 function l20 pr10b i/o k20 pr10c i/o k19 pr10d i/o k18 peckr i-eckr k17 pr9b i/o j20 pr9c i/o j19 pr9d i/o j18 pr8a i/o j17 pr8b i/o h20 pr8c i/o h19 pr8d i/o h18 pr7a i/o-cs1 g20 pr7b i/o g19 pr7c i/o f20 pr7d i/o g18 pr6a i/o-cs0 f19 pr6b i/o e20 pr5b i/o g17 pr5d i/o f18 pr4a i/o-rd /mpi_strb e19 pr4b i/o d20 pr4d i/o e18 pr3a i/o d19 pr2a i/o-wr c20 pr2b i/o e17 pr2c i/o d18 pr2d i/o c19 pr1a i/o b20 pr1b i/o c18 pr1c i/o b19 pr1d i/o a20 rd_cfgn rd_cfg a19 pt18d i/o-seckur b18 pt18c i/o pin or3tp12 function b17 pt18b i/o c17 pt18a i/o d16 pt17d i/o-rdy/rclk/mpi_ale a18 pt17a i/o a17 pt16d i/o c16 pt16c i/o b16 pt16a i/o a16 pt15d i/o-d7 c15 pt15a i/o d14 pt14d i/o b15 pt14a i/o a15 pt13d i/o c14 pt13b i/o-d6 b14 pt13a i/o a14 pt12d i/o c13 pt12c i/o b13 pt12b i/o a13 pt12a i/o-d5 d12 pt11d i/o c12 pt11c i/o b12 pt11b i/o a12 pt11a i/o-d4 b11 peckt i-eckt c11 pt10c i/o a11 pt10b i/o a10 pt10a i/o-d3 b10 pt9d i/o c10 pt9c i/o d10 pt9b i/o a9 pt9a i/o-d2 b9 pt8d i/o-d1 c9 pt8c i/o d9 pt8b i/o a8 pt8a i/o-d0/din
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 106 lucent technologies inc. lattice semiconductor pin information (continued) ta b le 42. or3tp12 256-pin pbga pinout (continued) pin or3tp12 function b8 pt7d i/o c8 pt7c i/o a7 pt7b i/o b7 pt7a i/o-dout a6 pt6d i/o c7 pt6a i/o b6 pt5c i/o a5 pt5a i/o-tdi d7 pt4d i/o c6 pt4a i/o b5 pt3d i/o a4 pt3a i/o-tms c5 pt2d i/o b4 pt2c i/o a3 pt2b i/o d5 pt2a i/o c4 pt1d i/o b3 pt1c i/o b2 pt1b i/o a2 pt1a i/o-tck c3 rd_data rd_data/tdo a1 v ss v ss d4 v ss v ss d8 v ss v ss d13 v ss v ss d17 v ss v ss h4 v ss v ss h17 v ss v ss n4 v ss v ss n17 v ss v ss u4 v ss v ss pin or3tp12 function u8 v ss v ss u13 v ss v ss u17 v ss v ss j9 v ss v ss j10 v ss v ss j11 v ss v ss j12 v ss v ss k9 v ss v ss k10 v ss v ss k11 v ss v ss k12 v ss v ss l9 v ss v ss l10 v ss v ss l11 v ss v ss l12 v ss v ss m9 v ss v ss m10 v ss v ss m11 v ss v ss m12 v ss v ss d6 v dd v dd d11 v dd v dd d15 v dd v dd f4 v dd v dd f17 v dd v dd k4 v dd v dd l17 v dd v dd r4 v dd v dd r17 v dd v dd u6 v dd v dd u10 v dd v dd u15 v dd v dd
lucent technologies inc. 107 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pin information (continued) ta b le 43. or3tp12 352-pin pbga pinout pin or3tp12 function b1 pl1d i/o c2 pl1c i/o c1 pl1b i/o d2 pl1a i/o d3 pl2d i/o-a0/mpi_be0 d1 pl2c i/o e2 pl2b i/o e4 ? nc e3 pl2a i/o e1 pl3d i/o f2 pl3c i/o g4 pl3b i/o f3 pl3a i/o f1 pl4d i/o g2 pl4c i/o g1 pl4b i/o g3 pl4a i/o-a1/mpi_be1 h2 pl5d i/o j4 pl5c i/o h1 pl5b i/o h3 pl5a i/o-a2 j2 pl6d i/o j1 pl6c i/o k2 pl6b i/o j3 pl6a i/o-a3 k1 pl7d i/o k4 pl7c i/o l2 pl7b i/o k3 pl7a i/o-a4 l1 pl8d i/o-a5 m2 pl8c i/o m1 pl8b i/o l3 pl8a i/o-a6 n2 peckl i-eckl m4 pl9c i/o n1 pl9b i/o m3 pl9a i/o-a7/mpi_clk pin or3tp12 function p2 pl10d i/o p4 pl10c i/o p1 pl10b i/o n3 pl10a i/o-a8/mpi_rw r2 pl11d i/o-a9/mpi_a ck p3 pl11c i/o r1 pl11b i/o t2 pl11a i/o-a10/mpi_b r3 pl12d i/o t1 pl12c i/o r4 pl12b i/o u2 pl12a i/o-a11/mpi_irq t3 pl13d i/o-a12 u1 pl13c i/o u4 pl13b i/o-seckll v2 pl13a i/o u3 pl14d i/o v1 pl14c i/o w2 pl14b i/o-a13 w1 pl14a i/o v3 pl15d gntn (pci) y2 pl15c c_ben7 (pci) w4 pl15b reqn (pci) y1 pl15a c_ben6 (pci) w3 pl16d ad31 (pci) aa2 pl16c c_ben5 (pci) y4 pl16b c_ben4 (pci) aa1 pl16a nc y3 pl17d nc ab2 pl17c nc ab1 pl17b nc aa3 pl17a ad30 (pci) ac 2 pl18d ad63 (pci) ab4 pl18c ad29 (pci) ac 1 pl18b ad62 (pci) ab3 ? nc ad2 ? nc
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 108 lucent technologies inc. lattice semiconductor pin or3tp12 function ac 3 pl18a ad28 (pci) ad1 cclk cclk af2 pb1a r stn (pci) ae3 ? nc af3 pb1b ad61 (pci) ae4 pb1c ad60 (pci) ad4 pb1d intan (pci) af4 pb2a vio (pci) ae5 pb2b ad59 (pci) ac 5 pb2c ad58 (pci) ad5 pb2d ad27 (pci) af5 pb3a ad57 (pci) ae6 pb3b ad56 (pci) ac 7 pb3c ad55 (pci) ad6 pb3d ad26 (pci) af6 pb4a ad54 (pci) ae7 pb4b ad53 (pci) af7 pb4c ad52 (pci) ad7 pb4d ad25 (pci) ae8 pb5a ad24 (pci) ac 9 pb5b idsel (pci) af8 pb5c ad51 (pci) ad8 pb5d ad23 (pci) ae9 pb6a ad22 (pci) af9 pb6b ad21 (pci) ae10 pb6c ad50 (pci) ad9 pb6d ad20 (pci) af10 pb7a ad19 (pci) a c10 pb7b ad18 (pci) ae11 pb7c ad17 (pci) ad10 pb7d ad16 (pci) af11 pb8a c_ben3 (pci) ae12 pb8b c_ben2 (pci) af12 pb8c trdyn (pci) ad11 pb8d ack64n (pci) ae13 pb9a req64n (pci) pin or3tp12 function a c12 pb9b irdyn (pci) af13 pb9c devseln (pci) ad12 pb9d stopn (pci) ae14 peckb c lk (pci) a c14 pb10b framen (pci) af14 pb10c perrn (pci) ad13 pb10d serrn (pci) ae15 pb11a nc ad14 pb11b par (pci) af15 pb11c c_ben1 (pci) ae16 pb11d c_ben0 (pci) ad15 pb12a hdc af16 pb12b ad15 (pci) a c15 pb12c ad14 (pci) ae17 pb12d ad13 (pci) ad16 pb13a ldc af17 pb13b ad49 (pci) a c17 pb13c ad48 (pci) ae18 pb13d ad12 (pci) ad17 pb14a ad11 (pci) af18 pb14b ad47 (pci) ae19 pb14c ad46 (pci) af19 pb14d ad10 (pci) ad18 pb15a init ae20 pb15b ad45 (pci) a c19 pb15c ad44 (pci) af20 pb15d ad9 (pci) ad19 pb16a nc ae21 pb16b ad43 (pci) a c20 pb16c ad42 (pci) af21 pb16d ad8 (pci) ad20 pb17a ad7 (pci) ae22 pb17b ad41 (pci) af22 pb17c ad40 (pci) ad21 pb17d ad6 (pci) ae23 ? nc pin information (continued) ta b le 43. or3tp12 352-pin pbga pinout (continued)
lucent technologies inc. 109 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pin or3tp12 function a c22 pb18a ad5 (pci) af23 pb18b ad39 (pci) ad22 pb18c ad38 (pci) ae24 ? nc ad23 pb18d ad4 (pci) af24 done done ae26 reset reset ad25 prgm prgm ad26 pr18a m0 a c25 pr18b ad37 (pci) a c24 pr18c enumn (pci) a c26 pr18d ledn (pci) ab25 pr17a ad36 (pci) ab23 pr17b ad3 (pci) ab24 pr17c ad35 (pci) ab26 pr17d ad34 (pci) aa25 pr16a ad2 (pci) y23 pr16b ad33 (pci) aa24 pr16c ad32 (pci) aa26 pr16d ad1 (pci) y25 pr15a ad0 (pci) y26 pr15b par64n (pci) y24 pr15c ejectsw (pci) w25 pr15d m1 v23 pr14a i/o w26 pr14b i/o w24 pr14c i/o v25 pr14d i/o v26 pr13a i/o u25 pr13b i/o v24 pr13c i/o u26 pr13d i/o u23 pr12a i/o-m2 t25 pr12b i/o u24 pr12c i/o t26 pr12d i/o pin or3tp12 function r25 pr11a i/o-m3 r26 pr11b i/o t24 pr11c i/o p25 pr11d i/o r23 pr10a i/o p26 pr10b i/o r24 pr10c i/o n25 pr10d i/o n23 peckr i-eckr n26 pr9b i/o p24 pr9c i/o m25 pr9d i/o n24 pr8a i/o m26 pr8b i/o l25 pr8c i/o m24 pr8d i/o l26 pr7a i/o-cs1 m23 pr7b i/o k25 pr7c i/o l24 pr7d i/o k26 pr6a i/o-cs0 k23 pr6b i/o j25 pr6c i/o k24 pr6d i/o j26 pr5a i/o h25 pr5b i/o h26 pr5c i/o j24 pr5d i/o g25 pr4a i/o-rd /mpi_strb h23 pr4b i/o g26 pr4c i/o h24 pr4d i/o f25 pr3a i/o g23 pr3b i/o f26 pr3c i/o g24 pr3d i/o pin information (continued) ta b le 43. or3tp12 352-pin pbga pinout (continued)
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 110 lucent technologies inc. lattice semiconductor pin information (continued) ta b le 43. or3tp12 352-pin pbga pinout (continued) pin or3tp12 function e25 pr2a i/o-wr e26 pr2b i/o f24 ? nc d25 pr2c i/o e23 pr2d i/o d26 pr1a i/o e24 pr1b i/o c25 pr1c i/o d24 pr1d i/o c26 rd_cfg rd_cfg a25 pt18d i/o-seckur b24 pt18c i/o a24 ? nc b23 pt18b i/o c23 pt18a i/o a23 pt17d i/o-rdy/rclk/mpi_ale b22 pt17c i/o d22 pt17b i/o c22 pt17a i/o a22 pt16d i/o b21 pt16c i/o d20 pt16b i/o c21 pt16a i/o a21 pt15d i/o-d7 b20 pt15c i/o a20 pt15b i/o c20 pt15a i/o b19 pt14d i/o d18 pt14c i/o a19 pt14b i/o c19 pt14a i/o b18 pt13d i/o a18 pt13c i/o b17 pt13b i/o-d6 c18 pt13a i/o a17 pt12d i/o pin or3tp12 function d17 pt12c i/o b16 pt12b i/o c17 pt12a i/o-d5 a16 pt11d i/o b15 pt11c i/o a15 pt11b i/o c16 pt11a i/o-d4 b14 peckt i-eckt d15 pt10c i/o a14 pt10b i/o c15 pt10a i/o-d3 b13 pt9d i/o d13 pt9c i/o a13 pt9b i/o c14 pt9a i/o-d2 b12 pt8d i/o-d1 c13 pt8c i/o a12 pt8b i/o b11 pt8a i/o-d0/din c12 pt7d i/o a11 pt7c i/o d12 pt7b i/o b10 pt7a i/o-dout c11 pt6d i/o a10 pt6c i/o d10 pt6b i/o b9 pt6a i/o c10 pt5d i/o a9 pt5c i/o b8 pt5b i/o a8 pt5a i/o-tdi c9 pt4d i/o b7 pt4c i/o d8 pt4b i/o a7 pt4a i/o c8 pt3d i/o
lucent technologies inc. 111 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pin information (continued) ta b le 43. or3tp12 352-pin pbga pinout (continued) pin or3tp12 function b6 pt3c i/o d7 pt3b i/o a6 pt3a i/o-tms c7 pt2d i/o b5 pt2c i/o a5 pt2b i/o c6 ? nc b4 ? nc d5 pt2a i/o a4 pt1d i/o c5 pt1c i/o b3 pt1b i/o c4 pt1a i/o-tck a3 rd_data rd_data/tdo a1 v ss v ss a2 v ss v ss a26 v ss v ss a c13 v ss v ss a c18 v ss v ss a c23 v ss v ss ac4 v ss v ss ac8 v ss v ss ad24 v ss v ss ad3 v ss v ss ae1 v ss v ss ae2 v ss v ss ae25 v ss v ss af1 v ss v ss af25 v ss v ss af26 v ss v ss b2 v ss v ss b25 v ss v ss b26 v ss v ss c24 v ss v ss c3 v ss v ss d14 v ss v ss pin or3tp12 function d19 v ss v ss d23 v ss v ss d4 v ss v ss d9 v ss v ss h4 v ss v ss j23 v ss v ss n4 v ss v ss p23 v ss v ss v4 v ss v ss w23 v ss v ss l11 v ss v ss l12 v ss v ss l13 v ss v ss l14 v ss v ss l15 v ss v ss l16 v ss v ss m11 v ss v ss m12 v ss v ss m13 v ss v ss m14 v ss v ss m15 v ss v ss m16 v ss v ss n11 v ss v ss n12 v ss v ss n13 v ss v ss n14 v ss v ss n15 v ss v ss n16 v ss v ss p11 v ss v ss p12 v ss v ss p13 v ss v ss p14 v ss v ss p15 v ss v ss p16 v ss v ss r11 v ss v ss r12 v ss v ss
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 112 lucent technologies inc. lattice semiconductor pin or3tp12 function r13 v ss v ss r14 v ss v ss r15 v ss v ss r16 v ss v ss t11 v ss v ss t12 v ss v ss t13 v ss v ss t14 v ss v ss t15 v ss v ss t16 v ss v ss aa23 v dd v dd aa4 v dd v dd a c11 v dd v dd a c16 v dd v dd a c21 v dd v dd ac6 v dd v dd d11 v dd v dd d16 v dd v dd d21 v dd v dd d6 v dd v dd f23 v dd v dd f4 v dd v dd l23 v dd v dd l4 v dd v dd t23 v dd v dd t4 v dd v dd pin information (continued) ta b le 43. or3tp12 352-pin pbga pinout (continued)
lucent technologies inc. 113 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pa ck ag e thermal characteristics summary there are three thermal parameters that are in com- mon use: ja , jc, and jc . it should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system air ow. ja this is the thermal resistance from junction to ambient (theta-ja, r-theta, etc.). where t j is the junction temperature, t a is the ambient air temperature, and q is the chip power. experimentally, ja is determined when a special ther- mal test die is assembled into the package of interest, and the part is mounted on the thermal test board. the diodes on the test chip are separately calibrated in an ov en. the package/board is placed either in a jedec natural convection box or in the wind tunnel, the latter f or forced convection measurements. a controlled amount of power (q) is dissipated in the test chip?s heater resistor, the chip?s temperature (t j ) is deter- mined by the forward drop on the diodes, and the ambi- ent temperature (t a ) is noted. note that ja is e xpressed in units of c/watt. jc this jedec designated parameter correlates the junc- tion temperature to the case temperature. it is generally used to infer the junction temperature while the device is operating in the system. it is not considered a true thermal resistance, and it is de ned by: where t c is the case temperature at top dead center, t j is the junction temperature, and q is the chip power. during the ja measurements described above, besides the other parameters measured, an additional temperature reading, t c , is made with a thermocouple attached at top-dead-center of the case. jc is also e xpressed in units of c/watt. jc this is the thermal resistance from junction to case. it is most often used when attaching a heat sink to the top of the package. it is de ned by: the parameters in this equation have been de ned above. however, the measurements are performed with the case of the part pressed against a water- cooled heat sink to draw most of the heat generated by the chip out the top of the package. it is this difference in the measurement process that differentiates jc from jc. jc is a true thermal resistance and is e xpressed in units of c/watt. jb this is the thermal resistance from junction to board ( jb ). it is de ned by: where t b is the temperature of the board adjacent to a lead measured with a thermocouple. the other param- eters on the right-hand side have been de ned above. this is considered a true thermal resistance, and the measurement is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads. note that jb is expressed in units of c/watt, and that this parameter and the way it is mea- sured are still in jedec committee. fpga maximum junction temperature once the power dissipated by the fpga has been determined (see the estimating power dissipation sec- tion), the maximum junction temperature of the fpga can be found. this is needed to determine if speed der- ating of the device from the 85 c junction temperature used in all of the delay tables is needed. using the maximum ambient temperature, t amax , and the power dissipated by the device, q (expressed in c), the max- imum junction temperature is approximated by: t jmax = t amax + (q ? ja ) ta b le 44 lists the thermal characteristics for all pack- ages used with the orca or3tp12 series of fpgas. ja t j t a ? q ------------------- - = jc t j t c ? q -------------------- = jc t j t c ? q -------------------- = jb t j t b ? q ------------------- - =
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 114 lucent technologies inc. lattice semiconductor pa ck ag e thermal characteristics tab le 44 . orca or3tp12 plastic package thermal guidelines 1. mounted on a 4-layer jedec standard test board with two power/ground planes. 2. with thermal balls connected to board ground plane. 3. the value of y jc f or all packages is <1 c/w. pa ck ag e coplanarity the coplanarity limits of the orca series 3/3+ packages are as follows: pbga: 8.0 mils pa ck ag e parasitics the electrical performance of an ic package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. table 45 lists eight parasitics associated with the orca packages. these parasitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. f our inductances in nh are listed: l sw and l sl, the self-inductance of the lead; and l mw and l ml , the mutual inductance to the nearest neighbor lead. these parameters are important in determining ground bounce noise and inductive crosstalk noise. three capacitances in pf are listed: c m , the mutual capacitance of the lead to the near- est neighbor lead; and c 1 and c 2 , the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). these parameters are important in determining capacitive crosstalk and the capacitive loading effect of the lead. resistance values are in mw. the parasitic values in table 45 are for the circuit model of bond wire and package lead parasitics. if the mutual capacitance value is not used in the designer?s model, then the value listed as mutual capacitance should be added to each of the c 1 and c 2 capacitors. package 1 ja ( c/w) t a = 70 c max t j = 125 c max 0 fpm (w) 0 fpm 200 fpm 500 fpm 256-pin pbga 2, 3 22.5 19.0 17.5 2.4 352-pin pbga 2, 3 19.0 16.0 15.0 2.9
lucent technologies inc. 115 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pa ck ag e parasitics (continued) tab le 45. orca or3tp12 package parasitics 5-3862(c)r2 figure 46. package parasitics package t ype l sw l mw r w c 1 c 2 c m l sl l ml 256-pin pbga 5.0 2.0 220 1.0 1.0 1.0 5?13 2?6 352-pin pbga 5.0 2.0 220 1.5 1.5 1.5 7?17 3?8 pad n l sw r w circuit board pad c m c 1 l sw r w l sl l mw c 2 c 1 l ml c 2 l sl pad n + 1
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 116 lucent technologies inc. lattice semiconductor pa ck ag e outline diagrams t erms and de nitions basic size (bsc): the basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. design size: the design size of a dimension is the actual size of the design, including an allowance for t and tolerance. t ypical (typ): when speci ed after a dimension, this indicates the repeated design size if a tolerance is speci ed or repeated basic size if a tolerance is not speci ed. reference (ref): the reference dimension is an untoleranced dimension used for informational purposes only. it is a repeated dimension or one that can be derived from other values in the drawing. minimum (min) or maximum (max): indicates the minimum or maximum allowable size of a dimension.
lucent technologies inc. 117 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor pa ck ag e outline diagrams (continued) 256-pin pbga dimensions are in millimeters. 5-4406(f) 0.36 0.04 1.17 0.05 2.13 0.19 seating plane solder ball 0.60 0.10 0.20 pwb mold compound 27.00 0.20 27.00 0.20 24.00 +0.70 ?0.00 24.00 +0.70 ?0.00 a1 ball identifier zone a b c d e f g h j k l m y n p r t u v w 12345678910 11 12 13 14 15 16 17 18 20 19 center array for thermal enhancement 19 spaces @ 1.27 = 24.13 a1 ball corner 19 spaces @ 1.27 = 24.13 0.75 0.15
orca or3tp12 fpsc data sheet embedded master/target pci interface october 2003 118 lucent technologies inc. lattice semiconductor pa ck ag e outline diagrams (continued) 352-pin pbga dimensions are in millimeters. 5-4407(f) 0.56 0.06 1.17 0.05 2.33 0.21 seating plane solder ball 0.60 0.10 0.20 pwb mold compound 35.00 +0.70 ?0.00 30.00 a1 ball identifi er zone af ae ad ac ab aa y w v u t r g 25 spaces @ 1.27 = 31.75 p n m l k j h 123 4 56 7 8910 12 1 416 18 2 22426 20 11 13 15 17 21 19 23 25 f e d c b a center array 25 spaces a1 ball 0.75 0.15 35.00 0.20 30.00 +0.70 ?0.00 0.20 @ 1.27 = 31.75 for thermal enhancement corner
lucent technologies inc. 119 data sheet orca or3tp12 fpsc october 2003 embedded master/target pci interface lattice semiconductor ordering information ta b le 46. ordering information device family part number speed grade package t ype ball count grade pa c king designator or3tp12 or3tp127ba256-db 7 pbga 256 c db OR3TP127BA352-DB 7 pbga 352 c db or3tp126ba256-db 6 pbga 256 c db or3tp126ba352-db 6 pbga 352 c db or3tp126ba256i-db 6 pbga 256 i db device type or3t xx x xx xx xxx packing designator db = dry packed tray embedded core type p1 ?32-/64-bit, 33/66mhz pci bus interface package type ba = plastic ball grid array (pbga) pin/ball count speed grade x grade blank = commercial i = industrial x fpsc base array 2 = or3t55 based 14x18 array

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